TechReport on Barcelona

[Hornet331]

wow thats sure nice to hear.

[alfaunits]

I'm 90% certain there will be a UDIMM (non registered) version... 100% sure there is a RDIMM only version.

When and how much!? :-)

[savantu]

When and how much!? :-)

November.

Cheap DP segment.

[savantu]

The B2 chips still has the memory controller bugs.

According to Graham, the BA stepping solves the memory performance issues.

Just look at the review! You can tell something is wrong with the memory performance of these chips.

What ? From what I see they are better than the K8 with the same memory.

The latency benches that Tech-Report conducted were abismal.

Well , my dear Watson , there is an L3 on chip now which can add up to 38ns of latency.Did you expect no trade offs whatsoever ?

The SSE optimized benches also weren't up to par, considering the doubled SSE throughput.

I think you need to visit an eye specialist.

~3.7x with 2x the cores


~3x with 2x the cores


Where does it say that K10s SSE units must have the same throughoutput as Core's ?

IIRC , K10 has 2 SSE units and Core has 3.In other words Core has better INT/FPU power and it shows .

K8/10 show better FPU power than Core sometimes , not because they have more resources , but due to better memory BW+latency.FP apps like huge memory BW.

If this is the final performance we can expect from the K10, then AMD screwed up horribly.

Don't tell me you believed there's some magic dust inside ?

[Richie P]

I may be wrong, please correct me if i am

from what i've read the l3 cache is a spilloff cache, and the memory controller feeds the l2, so the CPU isn't held up by the l3 latency (which would result in a pretty bad performance hit). cache latency (seconds) = latency (clocks) * duration of a clock (seconds)

and duration of a clock (seconds) = 1/frequency (to get seconds per cycle instead of cycles per second)

so latency (clocks) = latency (seconds) / (1/frequency) = latency (seconds) * frequency

using 23ns @ 2ghz, 19ns @ 2.5ghz:
(23*10^-9)*(2*10^9) = 46 clocks
(19*10^-9)*(2.5*10^9) = 47.5 clocks

latency in clockcycles increased going to 2.5ghz, there's no way you'll get better than linear scaling... that was a myth

Sorry to dig a mildly old thread, but I wanted to thank hollo for teaching me in such a nice and informative way. I didn't claim to know everything and wanted to be corrected if there was something I missed, so thank you

[Shintai]

Just because AMD aint super crown of the CPUs doesnt mean they are screwed. Try ask Intel how many 3Ghz quads they sell. Its not alot.

What you need is a product you can make with competitive price/performance in the high volume segments.

Ofcource K10 aint looking good on that due to its monolithic diesize. But atleast AMD got the hint for the next time and going the MCM way with all its designs.

K10 now needs better yields and faster speed. There is no magic steppings, broken SSE/FP or whatever. Its also a demonstration on there is a difference between a 1-1.5B$ R&D budget and a 5.5-6B$ R&D.

Only 2 things to blame, native design and the now doubleedged sword of SOI that strikes back.

Had AMD started with MCM K8 quads and then later on MCM K10s from the start they would be in an alot better situation on that alone. 150$ 2X2 brisbanes with a higher margin that would sell like ice melts in mexico. Along with staying with the bulk design and forget IBMs more or less exotic approaches. Just like Sony got caught in the Cell nightmare. Then AMD would simply sit with better cards today.

In short, fire Hector

Oh, and left ATI to die slowly as they were. What a waste of cash. Else they could have picked ATI up today for 1/3th of the price.

[doompc]

using 23ns @ 2ghz, 19ns @ 2.5ghz:
(23*10^-9)*(2*10^9) = 46 clocks
(19*10^-9)*(2.5*10^9) = 47.5 clocks

NB clock doesn't increase equal to CPU clock.
L3 cache latency must increase @ higher CPU Clock.

[xlink]

i see later revisions offering 5-20% greater performance per clock and scaling to 3Ghz. let's see if AMD can have that within 6months ... because that's when I'm upgrading...

[Zytek_Fan]

Sign me up for 2 of the 2.4ghz ones.

[Hornet331]

i see later revisions offering 5-20% greater performance per clock and scaling to 3Ghz. let's see if AMD can have that within 6months ... because that's when I'm upgrading...

20% higher ipc....

even intel only claimed an avarage 10% ipc increase with penryn (which is in reallity between 5-<10%) and that thing is by far more then a core revision...

your quite optemistic.

i can see higher clocks and the lower voltages and maybe a moderate ipc advantage in the 1-3% range, but 20%... wow.