TechReport on Barcelona

[hollo]

From what I understand, what Jacky was getting at with the cache latencies being reduced at a high clockspeed is actually correct. When going to RAM, the processor has to go through all the cache levels of the processor, including the 'slow' L3.

from what i've read the l3 cache is a spilloff cache, and the memory controller feeds the l2, so the CPU isn't held up by the l3 latency (which would result in a pretty bad performance hit).

The latency of the L3 cache is proportional to a speed (not sure on the terminology) that is increased when the clockspeed is raised. Therefore, with figures quote on the Tech Report site, the cache latecies are 23ns on the slower 2.0Ghz chip and 19ns on the faster (2.5Ghz) chip.

Therefore, increasing the clockspeed could result in what would seem a higher IPC.

cache latency (seconds) = latency (clocks) * duration of a clock (seconds)

and duration of a clock (seconds) = 1/frequency (to get seconds per cycle instead of cycles per second)

so latency (clocks) = latency (seconds) / (1/frequency) = latency (seconds) * frequency

using 23ns @ 2ghz, 19ns @ 2.5ghz:
(23*10^-9)*(2*10^9) = 46 clocks
(19*10^-9)*(2.5*10^9) = 47.5 clocks

latency in clockcycles increased going to 2.5ghz, there's no way you'll get better than linear scaling... that was a myth