**Official DFI LanParty UT P35-T2R Review/Overclock/Guide Thread**

[chawks2]

See this link. OR abbreviated:

The mechanics behind the multiplier are more complex. Inside the CPU there's a phase locked loop (PLL) circuit that uses two dividers.

Put (relatively) simply, the FSB clock is applied to one input of a frequency comparator, the output from which drives a voltage controlled oscillator (VCO). The VCO is the actual configurable gadget which, left to its own devices, spits out approximately the right core clock frequency for the CPU.

The VCO can't be trusted to get it quite right, though, so its output is fed through the two dividers (two dividers let you have fractional multipliers; older processors that only handled integer multipliers have only one divider) that're set to the right ratio to recreate the bus clock from the VCO's output, assuming the VCO output is exactly right.

The output from the dividers goes to the second input of the frequency comparator I mentioned above. This closes the loop in the PLL; the comparator controls the VCO's input, and compares the VCO's divided output to the FSB speed it's supposed to perfectly match, and tweaks the VCO input if it doesn't. The circuit can thus very rapidly settle onto pretty much the exact frequency the processor's meant to run at.

More info taken from here.

Clock VCO Divider: This function is use to fix the clock generator’s divider and “NB Strap” by its jumper. Then, system wouldn’t be reboot again because it presumed itself is
not in an overclock status. (this function needs to cooperate with particular jumper)