**Official DFI LanParty UT P35-T2R Review/Overclock/Guide Thread**

[RLM]

C-N,

Interesting comments. I haven't tried with a duo core, so wasn't aware of the difference.

How does your vdimm read with the duo and the quad. Is there any difference between the two, including droop at load?

There's so many parameters it's hard to pin point a specific one. Wondering if due to the quad's draw, whether there's a voltage issue in anyway. For instance I've only really topped out at 1.65v on the NB, maybe it needs more

Anyway here is a 20 min blend test with the quad. Memory is Geil 8500 cas 4s. I think that the Gskill HZ's actually perform a bit more reliably on this board.

Some notes running up to this. Running the ram 1060mhz 4-4-4-12 (266/667 4:5) wasn't particularly stable and blend crashed the system. As I say I think maybe my geils are part of the problem there, but it's also a 1066 strap if I'm right??

With 1016mhz 4-4-4-12 (333/800 5:6) at auto performance level of 6, blend failed after a minute. I loosened the performance level to 7, before running the following blend test.... Note Halted rather than failed.

Q6600 GO 423x9 (3.8 ghz) Mem 1016mhz 4-4-4-12 Prime Blend Test

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Enabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 9x
- Target CPU Clock: 3807 Mhz
CPU Clock: 423
Boot Up Clock: AUTO
DRAM Speed: 333/800 (5:6)
- Target DRAM Speed: 1016
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control: 1.55000
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.49v (Allowing for droop -0.05 idle a further -0.04 load)
SB 1.05V Voltage: 1.15v
SB Core/CPU PLL Voltage: 1.95v
NB Core Voltage: 1.57v
CPU VTT Voltage: 1.55v
Vcore Droop Control: Disabled
Clockgen Voltage Control: 3.75v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 105
x CPU GTL 0/2 REF Volt: 105
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: NORMAL
- Enhance Addressing: NORMAL
- DIMM 1 CLK fine delay: Current 2 (empty slot)
- DIMM 2 CLK fine delay: Current 6
- DIMM 3 CLK fine delay: Current 2 (empty slot)
- DIMM 4 CLK fine delay: Current 7

CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 12
All Precharge to Act: AUTO (MSet Reads 4)
REF to ACT Delay (tRFC): AUTO (MSet Reads 42)
Performance Level: 7 (Auto sets to Perf to 6)
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 14 (Mset reads 13)
Rank Write to Read (tWTR): 13 (Mset reads 12)
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): AUTO (Mset reads 8)
Ranks Write to Write (tWRWR): AUTO (tends to default I believe at 6)
Ranks Read to Read (tRDRD): AUTO (tends to default I believe at 6)
Ranks Write to Read (tWRRD): AUTO (tends to default I believe at 5)
Read CAS# Precharge (tRTP): 4
ALL PRE to Refresh: AUTO (memset reads 2)

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled