K10 Scores starting to surface

[terrace215]

At least that shows that all cache levels are enabled.
(latency gets the size by measuring the access time, unlike cpuz that relies on the cpuid outputs)

Why do people question those results any longer? The anand guy later confirmed that these results are like the results they are seeing... and that people were likely to be disappointed until AMD can get the clock speeds up.

[Lightman]

Lets compare latencies!

My X2 5600+ at 1938MHz/784MHz 4-4-4-12-15 (I'm too lazy to do exact same settings at the moment)


Barcelona 2GHz/Reg. 667MHz 5-5-5??



What strikes is a lot higher access latencies to memory which is expected due to slower memory modules and dual socket nature of system. Now everybody know how well K8 scales in SuperPi with memory speed!

For sure C2D will still be king in that bench but at least Phenom is looking much better than K8!

Edit:
We also can see here much better L1 cache implementation in K10 (first two columns).

[cpuz]

What strikes is a lot higher access latencies to memory which is expected due to slower memory modules and dual socket nature of system. Now everybody know how well K8 scales in SuperPi with memory speed!

Don't forget that latencies are cumulated (memory = L3 miss + L2 miss + L1 miss)
Keeps being high anyway.

[xlink]

don't see why they can't just search all memory levels at once...

anyone care to inform me a to what prevents this?

[JumpingJack]

don't see why they can't just search all memory levels at once...

anyone care to inform me a to what prevents this?

Technically, they do.... on almost every cache access, it is called snooping. It also depends if it is inclusive or exclusive cache, if inclusive then there is no need to search lower memory as it is guaranteed to be in lower cache... also since AMD uses an exclusive cache, the L1 and L2 are pooled together, more or less i.e. the data in L1 does not need to be in L2, but the search for data is still top down.

http://www.ece.mtu.edu/faculty/btdav...s/ispass04.pdf

Nice explanation and comparision of inclusive vs exclusive cache. Skim through their conclusions, exclusive caches benefit most when caches are small and dimishes when caches grow larger -- exclusive caches are also more complex and require more control/complexed logic.

[BrowncoatGR]

I am just going by what was in AMD's latest roadmap:
http://pc.watch.impress.co.jp/docs/2.../kaigai_02.pdf
(Pg 42)
http://www.amd.com/us-en/assets/cont...ck_Bergman.pdf
(Pg 19)

Two different presenters, same conlcusion.... Phenom X2/X4 will have HT1.0 specification. It is speculation as to why, if AMD is indeed accurate, perhaps they do not understand their own plans.... I could guess, purely guessing, that HT3.0 is having issues and holding back clocks, so they may drop to 1.0 specs in order to get higher CPU clockspeed.

Some seem to think budapest will transistion to HT3.0.... but, unless AMD botched their presentation, it appears that it has been pushed.

No im quite sure HT3 was pushed back only for multisocket servers, not for the desktop.(basically socket F+ got delayed or canceled). Take a look at slide 13 in the pdf you posted

[JumpingJack]

No im quite sure HT3 was pushed back only for multisocket servers, not for the desktop.(basically socket F+ got delayed or canceled). Take a look at slide 13 in the pdf you posted

Interesting.... but Socket F+ cannot be delayed, if it were then the split power plane will not be functional...

[EvlUndrWareNome]

retail day is coming up

[adamsleath]

k10>k8; it's that simple.
i just want to see fps for games with oc'ed phenom X4 (et al.)
i really want that +5%:

& as i havent seen any amd quad results (ie re heat&oc) - i'm interested to see scaling/heat problems aswell.

Surely someone will have a rig setup in September?

[arisythila]

Core totally owns it in wPrime.

Let's wait for some Penryn scores.

your on crack....

My Q6600 @ 3.3GHz memory clock at 1200MHz 5-5-5 doesn't even score that low....

There is something faulty about that benchy.

[arisythila]

retail day is coming up

For Barcy... Not Phenom...

[nn_step]

For Barcy... Not Phenom...

Barcy works in Socket F and you have many Socket F boards to choose from, so what is your point

[red]

oh no you didn't just eyeroll him!

phenom box looks better ok that's why

[mAJORD]

your on crack....

My Q6600 @ 3.3GHz memory clock at 1200MHz 5-5-5 doesn't even score that low....

There is something faulty about that benchy.

They're both 8core systems Aristhila, that's why.

But no, it doesn't own it, as the xeon was @ 2.6ghz

[KTE]

It's botched,Phenom is HT3.0

And to the one dude who said that HT3.0 was pushed to 2009,he is wrong.All Phenoms are HT3.0 ready,the boards (RD790) support HT3.0(16 bit link width,5.2GT/s).The chips CAN and will work(100&#37 on AM2 motherboards and the HT scales back to HT1.0(What this does to performance is not clear ,yet).

For everyones information, look very carefully at the latest AMD roadmap.



I would say Phenom (only Agena) has HT 3.0 capability but disabled to work at HT 1.0 until the clocks are ramped up sometime late Q4. Clocks of approximately 2.4GHz I'm guessing which I expect around Xmas holiday period. I still expect Agena FX to have HT 3.0 fully working.

[Donnie27]

oh no you didn't just eyeroll him!

phenom box looks better ok that's why

Good one

[gundamit]

We just have to be patient and see.

Given the nature of overclockers patience is always going to be in short supply around here.

[savantu]

At least that shows that all cache levels are enabled.
(latency gets the size by measuring the access time, unlike cpuz that relies on the cpuid outputs)

Did you really expect otherwise ?

[NapalmV5]

any benchs on female cycles?

[Nedjo]

For everyones information, look very carefully at the latest AMD roadmap.

[mAJORD]

Well that makes about as much sense..

HT3 enabled CPU, HT3 chipset = HT1 platform?

[tictac]

but motherboard manufacture clearly state Phenom platform got HT 3.0

[tictac]

Why do you bother about the HT link for a 1P system? It can't make any difference in CPU & system performance. Maybe a minor, unnoticeable decrease in TDP.

Also, those who think that the HT link speed will make any difference in computing performance should test their K8 with reduced HTT multiplier to x1.

i think when equip with high bandwith device such as 4 x 2900XT in crossfire mode the connection between

4 x 2900XT <-> Chipset (RD790) <-> K10 Processors

does matter...

[tictac]

I agree, but do all the non-graphics tests performed by that guy from coolaler forum, and you'll notice 0(zero) difference in performance between x5 and x1 multiplier of the HTT link.

Agree
eah i think ... non-graphic test (super pi) dont even occupied that much bandwith ...

[JumpingJack]

i think when equip with high bandwith device such as 4 x 2900XT in crossfire mode the connection between

4 x 2900XT <-> Chipset (RD790) <-> K10 Processors

does matter...

It matters for this situation when textures are swapped from main memory to graphics memory and when CPU sends updated frame information for the scene rendering... but even then, current gen and older games do not consume enough HT BW to push it to the limits and bog down. If the graphics card is memory rich, it becomes a non-factor.

I have seen perhaps 4 or 5 FPS hit at 1x over 5x.... albiet I have only tested a few games (quake 4, FEAR, HL2: lost coast).

Other than that, HT is not part of the equation for computational output in a single socket, it servers IO only for HDs, keyboard, mouse, graphics card...