Quote Originally Posted by terrace215 View Post
http://img.coolaler.com.tw/images/jj...mckdzozmt1.jpg

15 cycle L2 is vs. 12 cycle Penryn L2 (for 6 TIMES the L2 cache per core)

45 cycle L3.
At least that shows that all cache levels are enabled.
(latency gets the size by measuring the access time, unlike cpuz that relies on the cpuid outputs)