Official Desktop Penryn Discussion Thread

[-thc-(cZ)]

Yes, there is some confusion on that and I think it's due to Intel having it's price cut on that day..Some may have mixed the 2 up.

Ooops, sorry guys with the 22nd NDA thing I was clearly thinking the price cut date, stupit..

But I couldn't check, 'cause the thread got removed..

Anyways, is there a date for NDA riddance yet?

[Donnie27]

OK quick question or riddle.

What's wrong with this?

http://anandtech.com/cpuchipsets/int...spx?i=2955&p=3

Date: March 28th, 2007
Topic: CPU & Chipset
Manufacturer: Intel
Author: Johan De Gelas

Nehalem Micro Architecture: Intel Embraces the IMC and IGP

Surprisingly, Intel gave away quite a few details about Nehalem. Although Nehalem is still based on the 4-issue Core architecture, it takes "multithreading" to a whole new level. First of all, Nehalem can contain up to eight cores per die. Combined with 2-way Simultaneous Multi-Threading (SMT or Hyper-Threading), you'll have the ability to execute up to 16 threads on one chip!

Nehalem will also use multi-level shared cache. Pat Gelsinger indicated that only the highest level of cache would be shared, meaning that Nehalem could very well have a similar cache hierarchy to AMD's Barcelona (independent L1/L2 caches per core, but a shared L3 cache). The power of each core is "dynamically managed" which might indicate that Nehalem goes one step further than AMD's Barcelona core: it could have independent power planes.

Nehalem will no longer use a FSB but a serial point to point interconnect. Even more revolutionary is the fact that Nehalem will have an integrated memory controller (IMC) and that the number of serial interconnects is variable (Intel's version of "HyperTransport"). Another potentially groundbreaking move is that some Nehalem CPUs will have a GPU integrated (Intel's version of "Fusion"). With an integrated memory controller, new interconnect, and potentially integrated graphics, Nehalem will obviously require a new socket.

[safan80]

OK quick question or riddle.

What's wrong with this?

http://anandtech.com/cpuchipsets/int...spx?i=2955&p=3

it's from march.

[Donnie27]

it's from march.

That's one!

[Donnie27]

The rest/start of that old item.

http://anandtech.com/cpuchipsets/int...spx?i=2955&p=1

[informal]

Ok slightly OT,but the edit button works for indefinite amount of time since original post,so you can use it to update your post and not post a new one after only 1 min (06:47 PM, 06:48 PM; previous page : 05:29 PM ,05:30 PM)

On topic,why did you post those already known news?Did Anand change something in them,or do they shed some new light on Penryn(and not Nehalem,since it's not Nehalem topic )

[ferds]

check this out guys.!!!

http://fanboyreview.blogspot.com/200...8-chipset.html

http://valid.x86-secret.com/show_oc.php?id=223878

[Donnie27]

check this out guys.!!!

http://fanboyreview.blogspot.com/200...8-chipset.html

http://valid.x86-secret.com/show_oc.php?id=223878

Yea baby!

[Donnie27]

Ok slightly OT,but the edit button works for indefinite amount of time since original post,so you can use it to update your post and not post a new one after only 1 min (06:47 PM, 06:48 PM; previous page : 05:29 PM ,05:30 PM)

On topic,why did you post those already known news?Did Anand change something in them,or do they shed some new light on Penryn(and not Nehalem,since it's not Nehalem topic )

You wrote all of that to just say "Please make one post?" WOW LOL!

Some of Penryn's tech will be carried over to Nehalem.

That's for folks like you talking about Anand is on Intel's payroll. The conclusion has every piece of AMD BS that often misquoted here as well. Intel used IMC before AMD copied Alpha's. Serial Point to Point~ EV6 would be like Alpha, NOT AMD, so is the cache setup LOL! How can Intel copy Fusion when Fusion is a copy of Timna itself LOL?

So all of their Penryn info depends on which person at their site is doing the reporting. Same thing goes for the Inq and others with multiple writers.

[informal]

What does AMD has to do with Penryn in intel sticky?You again bring on the flaim bait with Fusion and the likes ,which has zero to to with Penry thread!

You might look up to the posters like ferds ,who with smaller amount of posts post real news to this sticky.
And yes,edit button can be used to edit your posts so you don't spam this and other topics with zillion posts in 30 minutes.

Thanks ferds,never saw that Yorkfield pic before.That dude says he can't post benches now,so NDA must be still on.Hopefully that will change soon.

[Donnie27]

What does AMD has to do with Penryn in intel sticky?You again bring on the flaim bait with Fusion and the likes ,which has zero to to with Penry thread!

You might look up to the posters like ferds ,who with smaller amount of posts post real news to this sticky.
And yes,edit button can be used to edit your posts so you don't spam this and other topics with zillion posts in 30 minutes.

Thanks ferds,never saw that Yorkfield pic before.That dude says he can't post benches now,so NDA must be still on.Hopefully that will change soon.

Again, if you can't trust that info, you can't trust other the stuff.

[SLi_dog]

check this out guys.!!!

http://fanboyreview.blogspot.com/200...8-chipset.html

http://valid.x86-secret.com/show_oc.php?id=223878

heh heh heh, isn't that the same guy who photoshopped the Penryn CPU-Z for April Fools day? That was classic

This one looks genuine though

[Donnie27]

http://www.fudzilla.com/index.php?op...2234&Itemid=35

[Shadowmage]

OK quick question or riddle.

What's wrong with this?

http://anandtech.com/cpuchipsets/int...spx?i=2955&p=3

1. 8 cores on one die is suspect. I'm sure it's 4 core max, and 8 core will be MCP.

2. Independent power planes might be incorrect. That's a big 'MIGHT'.

Not too sure what else could be wrong. Why is the date incorrect?

I don't see why you are nitpicking over 'who did what first'. Even if Intel did something first, AMD came out with the first mainstream (mass-market) version and thus popularized the concept.

[Shintai]

Nehalem will "only" be 4 cores. 8 would be MCM. L3 cache? I dont see it. maybe on MP Xeons. There is no need due to shared cache. This aint K10.
The IMC and CSI for desktop is also a wrong one.

Nehalem with integrated GPUs. Possible with some mobile maybe. But I dont think so until 32nm.

Also the FB-DIMM would support DDR2, DDR3 etc. It doesnt matter since the memory controller only communicates with the AMB chip.

So overall, pretty wrong stuff. Unless ofcourse its me thats completely messed up.

[savantu]

Nehalem will "only" be 4 cores. 8 would be MCM. L3 cache? I dont see it. maybe on MP Xeons. There is no need due to shared cache. This aint K10.

Nehalem will have an L3 , shared for all the cores.Also , Pat Gelsinger said Nehalem was designed to have from 1 to 8 cores. ( I expect 8 cores to be 32nm )

The IMC and CSI for desktop is also a wrong one.

Not at all.This information is very bogus , based only on Charlie's post.All Intel slides claim Nehalem will have CSI and IMC , no distinction is made on this , but on integrated graphics.

[Blauhung]

"Nehalem" will only have 4 cores, there are Nehalem derivatives that are planned that have up to 8. The whole point of the new design was to have almost every portion of the die be interchangeable. the IMC can be removed (or possibly disabled), and cores can be added or removed from the raw layout relatively easily.

each of these derivatives will in turn come with a new reticle tapeout and product name.

[Donnie27]

1. 8 cores on one die is suspect. I'm sure it's 4 core max, and 8 core will be MCP.

2. Independent power planes might be incorrect. That's a big 'MIGHT'.

Not too sure what else could be wrong. Why is the date incorrect?

I don't see why you are nitpicking over 'who did what first'. Even if Intel did something first, AMD came out with the first mainstream (mass-market) version and thus popularized the concept.

Wrong is wrong=P Anyway, Nehalem is the So-Called native Quad Core Answer from Intel. Just more Marketing schlock (Native) IMHO! Remember MCM-ed Nehalem will not matter anyway since it will be Point to Point using CSI not a FSB. One Quad Core Penryn will not need an IMC. Current Q6xxx vs. $X$ (erum 4 X 4) pretty much proves that.

Intel had no reason to hide Penryn from any of us, shouldn't AMD have done the same? Penryn has Improvements over Conroe and looks it will be a sweet overclocker.

Edit; Added later, it will do 8 threads because it also includes Hyperthreading 2. 8-core models can process 16 single threads.

[Shadowmage]

You do know that the difference between 4x4 and Kentsfield is much, much, much more than the chip packaging, correct? Also, 4x4 is a dual socket model. You can't compare them like that.

I don't get what the last comment is for. The article said Nehalem will support up to 16 threads via hardware, ie it will have 8 cores. We already know the 4 core version will do 8 threads.

[onethreehill]

Intel to Launch 45nm Desktop Chips in Q4 – Documents.

Intel Corp. has decided to bring the launch of its 45nm quad-core chips forward to the fourth quarter of 2007. This will allow the company to be in full position to compete against the new family of products by its main rival Advanced Micro Devices.

http://www.xbitlabs.com/news/cpu/dis...801221842.html

[Speederlander]

Intel to Launch 45nm Desktop Chips in Q4 – Documents.

http://www.xbitlabs.com/news/cpu/dis...801221842.html

This is good enough to get it's own full thread really, rather than being stuck at the end of the Penryn thread.

[Donnie27]

You do know that the difference between 4x4 and Kentsfield is much, much, much more than the chip packaging, correct? Also, 4x4 is a dual socket model. You can't compare them like that.

I don't get what the last comment is for. The article said Nehalem will support up to 16 threads via hardware, ie it will have 8 cores. We already know the 4 core version will do 8 threads.

That was the only way to get 4 cores vs. 4. Soon that will changed. Oh, correction I mean one Woodcrest.

[SaII]

quad penryn confirmed

due Q4 '07
http://www.engadget.com/2007/08/02/i...-market-q4-07/

[Donnie27]

quad penryn confirmed

due Q4 '07
http://www.engadget.com/2007/08/02/i...-market-q4-07/

http://www.legitreviews.com/article/488/2/

The DivX results are particularly stunning, showing the power of SSE4 and what it will mean for applications that take advantage of the new instructions. The 3.33GHz Yorkfield processor is 52% faster than the 2.93GHz Kentsfield in this benchmark.

What I thought was more impressive was that the Dual Core Wolfdale was faster than the Q6850 QC But that's with Optimized software can do and you know we'll not see enough of that. Add to this that this was a real app and not some synthetic test. This series of tests were shown at multiple sites.

[XeRo]

http://theinquirer.net/?article=41468
http://www.fudzilla.com/index.php?op...=2289&Itemid=1