Nehalem will "only" be 4 cores. 8 would be MCM. L3 cache? I dont see it. maybe on MP Xeons. There is no need due to shared cache. This aint K10.
The IMC and CSI for desktop is also a wrong one.
Nehalem with integrated GPUs. Possible with some mobile maybe. But I dont think so until 32nm.
Also the FB-DIMM would support DDR2, DDR3 etc. It doesnt matter since the memory controller only communicates with the AMB chip.
So overall, pretty wrong stuff. Unless ofcourse its me thats completely messed up.
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