Quote Originally Posted by Shintai View Post
Nehalem will "only" be 4 cores. 8 would be MCM. L3 cache? I dont see it. maybe on MP Xeons. There is no need due to shared cache. This aint K10.
Nehalem will have an L3 , shared for all the cores.Also , Pat Gelsinger said Nehalem was designed to have from 1 to 8 cores. ( I expect 8 cores to be 32nm )

The IMC and CSI for desktop is also a wrong one.
Not at all.This information is very bogus , based only on Charlie's post.All Intel slides claim Nehalem will have CSI and IMC , no distinction is made on this , but on integrated graphics.