New Memory Tweaker for Intel Chipsets

[caesarean]

what's the question???? help with what?? looks like buffalo d9gkx

Question is,
@MemSet, Display 751.7Mhz
&
@CPU-Z, Display 644.3Mhz

Question is WHY?????, PLEASE

[ziddey]

Question is,
@MemSet, Display 751.7Mhz
&
@CPU-Z, Display 644.3Mhz

Question is WHY?????, PLEASE

nothing to worry about. trust cpuz.

you lowered your multiplier from 7 to 6. Here's how memset made the calculation:

default / actual x fsb / divider.

so in your case, 7 / 6 x 429 / 2 x 3 = 750

dont worry about it

[The Stilt]

It seems that there won´t be Memset or any similar programs for P35 or it´s successors.

The dram timing registers of Bearlake chipsets can be read and virtually written, but there is no real effect what so ever.

This is because the different dram timings are more or less tied together by several algorithms that are executed during memory initialization sequence.

In practice this means that the dram timings cannot be changed without resetting the mch. The timings can only be changed from the bios.

To prove a point, I changed dram timings to 1-3-3-7 (tCL-tRCD-tRP-tRAS) on the fly. It is clear that there is no such ram that can operate with those timings at DDR1000 (without mentioning P35 supporting tCL 1 Clocks).

CPU-Z Validation at DDR1000 with 1-3-3-7 timings

To prevent people from cheating in memory overclock / timing records none of this data will be published.

[harleybro]

It seems that there won´t be Memset or any similar programs for P35 or it´s successors.

Darn that is terrible news. Maybe bioses will eventually allow adjustments of all ram timings.

[FELIX]

It seems that there won´t be Memset or any similar programs for P35 or it´s successors.

The dram timing registers of Bearlake chipsets can be read and virtually written, but there is no real effect what so ever.

This is because the different dram timings are more or less tied together by several algorithms that are executed during memory initialization sequence.

In practice this means that the dram timings cannot be changed without resetting the mch. The timings can only be changed from the bios.

To prove a point, I changed dram timings to 1-3-3-7 (tCL-tRCD-tRP-tRAS) on the fly. It is clear that there is no such ram that can operate with those timings at DDR1000 (without mentioning P35 supporting tCL 1 Clocks).

CPU-Z Validation at DDR1000 with 1-3-3-7 timings

To prevent people from cheating in memory overclock / timing records none of this data will be published.

...I'm not surprised of that for tCL, it's already the same for P965 chipsets.
But for tRTC and others, it's a bad news... perhaps more infos in datasheets.

[The Stilt]

...I'm not surprised of that for tCL, it's already the same for P965 chipsets.
But for tRTC and others, it's a bad news... perhaps more infos in datasheets.

Yes, tCL is not a surprise, but everything else is "locked" too.
I doubt the datasheet will make any difference, since I have already talked with one of the chipset architects who was working on Bearlake.

[xgman]

It seems that there won´t be Memset or any similar programs for P35 or it´s successors.

The dram timing registers of Bearlake chipsets can be read and virtually written, but there is no real effect what so ever.

This is because the different dram timings are more or less tied together by several algorithms that are executed during memory initialization sequence.

In practice this means that the dram timings cannot be changed without resetting the mch. The timings can only be changed from the bios.

To prove a point, I changed dram timings to 1-3-3-7 (tCL-tRCD-tRP-tRAS) on the fly. It is clear that there is no such ram that can operate with those timings at DDR1000 (without mentioning P35 supporting tCL 1 Clocks).

CPU-Z Validation at DDR1000 with 1-3-3-7 timings

To prevent people from cheating in memory overclock / timing records none of this data will be published.

ouch!!! I was counting on Memset to come to the rescue here.