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Thread: K8l to have 6mb cache

  1. #51
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    Quote Originally Posted by Turtle 1
    Acually since 3 this morning I have read a lot. Visted my favorite forum. Assembled to C2D water cooled gamers. Installed software. prepared for shipping. So all and all been pretty busy this day.
    ugh.... just..

    seriously :/

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  2. #52
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    Quote Originally Posted by Turtle 1
    Acually since 3 this morning I have read a lot. Visted my favorite forum. Assembled to C2D water cooled gamers. Installed software. prepared for shipping. So all and all been pretty busy this day.
    so what did you spend the other 23 hours for then?
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  3. #53
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    Quote Originally Posted by Turtle 1
    Acually since 3 this morning I have read a lot. Visted my favorite forum. Assembled to C2D water cooled gamers. Installed software. prepared for shipping. So all and all been pretty busy this day.
    What, would you like a trophy or something?

  4. #54
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    Quote Originally Posted by agenda2005
    You can speculate whatever you like, but making up for 20% lag is quite a lot in the CPU world.

    Time will tell, but your 25% IPC improvement of K8L over Conroe is too ambitious IMHO. That is approximately 45% improvement per clock over K8. AMD will have to come out with a perfect design that will fill up the CPU pipeline and extensively utilize the 3 wide issue.

    Even Core 2 with its OoO and aggresive prefetchers is only able to sustain one issue per clock cycle. Aside from that Core 2 also have potentially higher clock to execute instructions.

    Go and read up man. AMD have their work cut out for them.
    Also i was kidding couse you put 4x512MB no 4x512kb as it should be

    do you know how much ipc improoved from p4 to c2d?

    why cant amd improove 25%? time will tell im not making up i got this info from the same person that told me 9 months before that:

    C2D would kill amd
    C2D would have cold bug
    C2D would get over 3.6GHz OC

    so i trust him
    Last edited by metro.cl; 11-28-2006 at 03:06 PM.

  5. #55
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    Quote Originally Posted by brentpresley
    Be kind to metro.

    I have a sneaky suspicion that he will (or has?) seen K8L before all but maybe 3-4 people here. Unfortunately, I'm sure NDA applies.

    That is why I take what he says seriously.
    lol i dont have such good friends as to see things but i get info from some of them

    lets debate that is the nice thing in forums i learn a lot from you guys i got into this world about 1.5 years ago only

  6. #56
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    Quote Originally Posted by brentpresley
    C2D cold bug? You left a NOT out of there right?
    they do with ln2

  7. #57
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    Any of your friends, metro.cl, saw Brisbane CPU in action?? Mayby you saw die shot accidentally? Any info will be welcome .
    Last edited by Lightman; 11-28-2006 at 03:22 PM.
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  8. #58
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    Quote Originally Posted by Lightman
    Any of your friend, metro.cl, saw Brisbane CPU in action?? Mayby you saw die shot accidentally? Any info will be welcome .
    one of them has one, i've been asking for a pic and some action to show, but they are playing with something else, he promised late November for a SS or some info of it.

    But so far it is just AM2 in 65nm

  9. #59
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    Quote Originally Posted by metro.cl
    one of them has one, i've been asking for a pic and some action to show, but they are playing with something else, he promised late November for a SS or some info of it.

    But so far it is just AM2 in 65nm
    THANKS for this info

    BTW keep asking him for pictures and mayby some OC session.
    PS. If I may ask, with what they are playing right now??
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  10. #60
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    Quote Originally Posted by brentpresley
    C2D cold bug? You left a NOT out of there right?
    yeah didn't you know?
    Fast computers breed slow, lazy programmers
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  11. #61
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    Quote Originally Posted by Lightman
    THANKS for this info

    BTW keep asking him for pictures and mayby some OC session.
    PS. If I may ask, with what they are playing right now??
    lol i dunno, but they got brisbane & 4300 and they wont play with any of them, so it must be something good

    tryed getting one from them but was a no go also

  12. #62
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    Quote Originally Posted by metro.cl
    they do with ln2
    Breaks bring browser to screaming hault. User screams LINK PLEASE!!!!!

  13. #63
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    Quote Originally Posted by Turtle 1
    Breaks bring browser to screaming hault. User screams LINK PLEASE!!!!!
    Just ask few guys here who use LN2

  14. #64
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    the should be 4xcores with 1MB L2 each and 2MB L3
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  15. #65
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    The stupid enquirer always come with something out to make the news to overflow.

    I wonder what they will win with all this

    By the way, if this is true I can't see it having 6 mb of cache.

  16. #66
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    Quote Originally Posted by Cooper
    Just ask few guys here who use LN2
    Man cooper I read almost every thread here and I have not once seen A report of coldbug. This does not refer to the news thread its all threads in most catogories.
    Last edited by Turtle 1; 11-28-2006 at 07:06 PM.

  17. #67
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    There isn`t any special "Conroe has cold bug" thread. And those certainly aren`t here in News section.

    Enough with offtopic already. Threa is about AMD K8L - not the Conroe cold bug

  18. #68
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    Quote Originally Posted by metro.cl
    Also i was kidding couse you put 4x512MB no 4x512kb as it should be

    do you know how much ipc improoved from p4 to c2d?

    why cant amd improove 25%? time will tell im not making up i got this info from the same person that told me 9 months before that:

    C2D would kill amd
    C2D would have cold bug
    C2D would get over 3.6GHz OC

    so i trust him
    Alright, thanks for the correction. I will wait and see what AMD can bring to the table.
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  19. #69
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    Quote Originally Posted by brentpresley
    As usual, your statement is a bit misleading and incomplete.

    K8 (like K8L) also has 3 complex decoders.

    C2D uses 1 complex and 3 simple decoders (4 total, for the math challenged).

    With C2D, in CERTAIN instances, two x86 instructions can be "fused" and operated on at once. So under optimal conditions there are 5 instructions issued at once, not just 4.

    Complex decoders are not the end-all be-all in the x86 world. They take up more die space than simple decoders and there are only SPECIFIC instances where they are useful (decoding longer instructions into subsets, etc.). Simple decoders take up less die space and work on the more common instructions seen in the CISC architecture.

    More about the K8 vs C2D architecture here:
    http://www.anandtech.com/cpuchipsets...oc.aspx?i=2748
    outch!!!! that makes these look pretty obsolete .......... amd will take a beating in 2007 big time it seems
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  20. #70
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    Quote Originally Posted by dinos22
    outch!!!! that makes these look pretty obsolete .......... amd will take a beating in 2007 big time it seems
    ummm, a little secret for you. Normal number of Integer operations is under two at a time.

    if you don't believe me. http://www.cpuid.com/perfmon.php
    Use the log function and find out for yourself
    Fast computers breed slow, lazy programmers
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    http://www.lighterra.com/papers/modernmicroprocessors/
    Modern Ram, makes an old overclocker miss BH-5 and the fun it was

  21. #71
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    Quote Originally Posted by nn_step
    ummm, a little secret for you. Normal number of Integer operations is under two.
    if you don't believe me. http://www.cpuid.com/perfmon.php
    Use the log function and find out for yourself
    it really is a pointless discussion without any benchmarks still so let's see what happens...........AMD is getting severely beaten at the moment. How long will we have to wait until a decent CPU for an extreme overclocker will come one
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  22. #72
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    umm if you didn't know the only weak point about AMD is the Floating point performance. Which from what we hear should be the new king
    Fast computers breed slow, lazy programmers
    The price of reliability is the pursuit of the utmost simplicity. It is a price which the very rich find most hard to pay.
    http://www.lighterra.com/papers/modernmicroprocessors/
    Modern Ram, makes an old overclocker miss BH-5 and the fun it was

  23. #73
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    Quote Originally Posted by brentpresley
    BS. My E6600 will spank the living CRAP out of anything AMD has to offer right now in terms of integer performance.

    You just make this garbage up as you go along don't you?
    i think he is saying that AMD is about to correct Integer floating point performance in new CPUs

    let's wait and see i say

    i'm going with whoever is fastest on the day. Right now Intel is a country mile ahead
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  24. #74
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    http://www.amd.com/us-en/assets/cont...alystDayV2.pdf

    there, take a look at that. im sure it would set a few of you clear on some info thats been going around at the inq :\

    about my previous post, i said it was 4mb of L2 cache...i was wrong it says 2+ in the tech docs i just linked to. so it will be 4x512kb + 2+kb. so thats a total of 4mb...not too shabby. just keep the latency low, and it should be more than good enough.

    i thought the 3/4 issue thing wasn't something to worry about? isn't it visible in the pictures of the core? eh, it better be 4. AMD did say that nothing about the K8 architecture went untouched. so...lets hope it really is a 4 issue core.
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  25. #75
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    ^^ Integer and FP operations are independent of each other. There's no such thing as "Integer floating point" operations.

    nn_step: AMD's FPU was and still is one of the best on the market. All Intel did was add 2 more to make 3. It's ALU and memory performance is what's lacking. The memory controller does make up for some of the problems though.
    oh man

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