Quote Originally Posted by Eldonko View Post
Not sure about this "bclk sweet spot" theory. What do you asus guys have to say about that?


Assuming there are no major differences in memory frequency, it is entirely possible that asking the internal PLL for a greater level of multiplication of the reference clock produces more phase error or increases jitter. If that were to be the case, increasing Vcore and tuning the voltage of any other related bus becomes necessary to counter any loss in sampling margin (may not always be successful either).