Quote Originally Posted by FlanK3r View Post
DB:whats mean in practice?
Pipeline is longer (as expected for a higher clockable design). This is also a reason for the cache latencies.

1 cycle lower FMA/FMUL/FADD latency is good for FP performance.

But the fast mode, mul latencies and even a 4 cycle latency for such a small L1 cache could be signs of some new clocking modes. If I find out more about that I'll surely post it