Quote Originally Posted by terrace215 View Post
Actually, if you're talking about BD "cores", not modules of 2 cores, the ipc and power will likely go down a little, as the core count goes up.

Think of it like:

Take K10 core. Now *share* the L1 and L2 and decode with a second core. (lower performance, but you get lower power). The FP is about the same (vs K10), double the width, but shared between the 2 cores. FMA will help some apps, clearly. But in general, I expect each core will have decreased IPC, power and area vs a K10 core, but they'll try to put more of them on a chip than with K10.
Bookmarked.

L1 D$ won't be shared, but L1 I$ will. Decoders will be less restricted than K10's, and wider. FPU will be very different, we have to see how it performs, but very likely with better performance per core than in K10, (with a probability more than 50%) even without FMA. Each core might have decreased IPC (not so likely), but overall design aims at better scalability. And more cores seems to be the way to go. Intel already demonstrated designs with tons of cores.