Here is my current setup.
No matter what I do it wont be stable at 500fsb. The settings below are stable.
CPU Ratio Setting: 8
FSB Strap to NB: 333
FSB Freq: 475
PCIE Freq: 105
DRAM Freq: 951
DRAM Command Rate : 2T
DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# ActivateTime : 12
RAS# to RAS# Delay : 3
Row Refresh Cycle Time : 55
Write Recovery Time : 6
Read to Precharge Time : 3
Read to Write Delay (S/D) : 8
Write to Read Delay (S) : 3
Write to Read Delay (D) : 5
Read to Read Delay (S) : 4
Read to Read Delay (D) : 6
Write to Write Delay (S) : 4
Write to Write Delay (D) : 6
Write to PRE Delay : 14
Read to PRE Delay : 5
PRE to PRE Delay : 1
ALL PRE to ACT Delay : 5
ALL PRE to REF Delay : 5
DRAM Static Read Control: Auto
Dram Read Training : Auto
MEM OC Charger : Enabled
Ai Clock Twister : Lighter
Transaction Booster : Manual
Common Performance Level [10]
Pull-In of CHA PH1 Disabled
Pull-In of CHA PH2 Disabled
Pull-In of CHA PH3 Disabled
Pull-In of CHA PH4 Disabled
Pull-In of CHA PH5 Disabled
Pull-In of CHB PH1 Disabled
Pull-In of CHB PH2 Disabled
Pull-In of CHB PH3 Disabled
Pull-In of CHB PH4 Disabled
Pull-In of CHB PH5 Disabled
CPU volt:1.32500
CPU PLL Voltage: 1.52650
NB Voltage: 1.35175
DRAM Voltage: 2.17100
FSB Termination Voltage: 1.31200
SB Voltage: 1.1
SB 1.5 Voltage: 1.5
CPU GTL Reference 0 : +20mv
CPU GTL Reference 1 : +20mv
CPU GTL Reference 2 : +20mv
CPU GTL Reference 3 : +20mv
North Bridge GTL Reference : AUTO
DDR2 Channel A REF Voltage : AUTO
DDR2 Channel B REF Voltage : AUTO
North Bridge DDR Reference : AUTO
Load Line Calabration : Enabled
CPU Sread Spectrum : Disabled
PCIE Spread Spectrum : Disabled
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