**Official DFI LanParty UT X48-T2R(and LT) Discussion

[merlin76]

you need the new bios which should be up soon, Oskar tuned the board to help overclocking PSC IC's like the ones we use on the 1066 reapers you quoted there.

I will try to post guides for these and the 1150 flex2 over at the ocz forum to help those looking for settings...BUT remember, im not interested in CPU overclocking so those who moan that they can not hit the CPU clocks with the ram where they want it will be asked to test with CPU's (quads especially) at near stock speeds due to the nature of the chipset.

I got my Flex II yesterday and so far they are working great with LT X38 and current BIOS (03/14). I'm very happy with it.

DDR2-1168 was the max stable clock I could achieve:


Although the screen shows tRD 8 it's 7, only one phase is running at 8.
My CPU does not like FSB higher than 460, so I'm a bit limited on dividers.

Memory settings used:

DRAM Timing
- Enhance Data transmitting: Normal
- Enhance Addressing: Normal
- T2 Dispatch: Enabled

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Relaxed
- DIMM 1 Clock fine delay: Current
- DIMM 2 Clock fine delay: Current
- Ch 1 Command fine delay: Current
- Ch 1 Control fine delay: Current

Ch2 Clock Crossing Setting: More Relaxed
- DIMM 3 Clock fine delay: Current
- DIMM 4 Clock fine delay: Current
- Ch 2 Command fine delay: Current
- Ch 2 Control fine delay: Current

Ch1Ch2 CommonClock Setting: More Relaxed

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL):5
RAS# to CAS# Delay (tRCD):5
RAS# Precharge (tRP):5
Precharge Delay (tRAS):15
All Precharge to Act: 6
REF to ACT Delay (tRFC): 54
Performance LVL (Read Delay) (tRD): 8

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Enabled
- Channel 1 Phase 1 Pull-In: Enabled
- Channel 1 Phase 2 Pull-In: Enabled
- Channel 1 Phase 3 Pull-In: Enabled
- Channel 1 Phase 4 Pull-In: Enabled

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Enabled
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Enabled
- Channel 2 Phase 3 Pull-In: Enabled
- Channel 2 Phase 4 Pull-In: Enabled

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 6

This could get my new 24/7 setting:


// Edit

I have been able to reduce tRD to 6, so performance improved a bit.



FSB266 and 266/1066 divider or FSB333 and 333/1066 divider did not cause any issues to me. DDR2-1200 was no go with current BIOS, I could get it nearly stable at DDR2-1192. Do you have any news on the new BIOS files with PSC IC optimizations?