Quote Originally Posted by Anemone View Post
Yep thanks for correcting my thinking, with QPI the FSB concept goes away. There must still be a ratio of core speed to memory speed though, I'd imagine. But it won't work the old way that's for sure.

I wouldn't have expected any EE chips on the mainstream platform.
Yes there will still be ratio's and multipliers to control everything with an on die/package PLL doing the clock generation. Memory will most likely be set to the highest platform supported SPD profile coded on the ram, and probably won't be user selectable.