I have been working on Bearlake for few weeks now.
I have collected some data that is required to make Memset support Bearlake chipset.
Asus especially has not make my work very easy since their bioses are doing something that they are not supposed to be doing
Anyway Felix has done some excellent work on the program, and it will be released soon.
While I was monitoring the changes in chipset registers I noticed something interesting when the motherboard changed the chipset "strap" (internal latencies).
Usually these latencies cannot be changed unless MCH is fully reseted.
(Or maybe we just didn´t figure out how)
Luckily Bearlake is different and the latency can be changed without resetting the MCH
The "strap" has ten different "stages"
1 is the tightest and 10 is pretty much super loose.
One is almost never used, but the second and third are quite common.
Asus actually uses the slowest possible value when booted at 533FSB, and so does Gigabyte at 417FSB or so.
With 1:1 divider at 533FSB Asus uses slower setting than at the same FSB with 6:5 divider. Both can be tweaked of course.
This feature will be added in Memset at some point.
At the mean time you can look at the results.
I used 5-5-5-9-25-5-8-2-2-5 (tCL-tRCD-tRP-tRAS-tRFC-tWR-tRD-tWTR-tRRD-tRTP) settings and 6:5 divider for Everest.
None of the timings were changed between the tests, just the "strap".
For SuperPI I had to use 1:1 divider because the ram isn´t able to pass SPI32M at DDR1280 with 2.55V. The timings however are identical.
The first test of Everest was run with level 8 setting and the last with level 5 setting.
The first SuperPI run was done at level 10 setting and the last (fastest) at level 6 setting.
See the difference?
Everest Cache & Memory Benchmark
Level 8 (boot value for 533FSB / 6:5 divider)
Click images for larger picture
Level 7
Level 6
Level 5 (tightest possible value at this frequency)
SuperPI 32M
Level 10 (boot value for 533FSB / 1:1 divider)
Level 9
Level 8
Level 7
Level 6 (tightest possible at 533FSB / 1:1)
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