AMD's Bobcat and Bulldozer

[Opteron146]

So on an AM3 system there are three things that could be called NB, the IMC, the uncore and the PCIe part of the chipset?
Usually the confusion tends to be about the chipset or the IMC, but dragging the uncore to the mix is just unnecessary.
The uncore has nothing to do with traditional NB-functions.

I would like to use uncore as umbrella term for everything outside of the CPUcore (or module):
HTr, IMC, L3, XBAR.
Currently it seems that
NB = XBAR + HTr (and in the future in the Llano case probably PCIe)

because everything else is mentioned separately.

Imo it is not important to mention the IMC or HT seperately, every CPU has it nowadays, be it triple channel and QPI for intel or dual channel and Hypertransport for AMD. No use to make a difference here and also no use in mentioning the IMC explicitly but not mentioning Hypertransport by hiding it with the NB term.

AMD should not invent new namimgs, they just should give proper statements, like in case with the AM3 compatibility ;-)

Life would be much easier, haha

[wez]

If the amount of months is around twelve or possibly more, then yes.

Well, the board is scheduled for September this year, and Bulldozer is due in ~Q1 2011?

[Olivon]

AMD Video - Bulldozer and Bobcat

http://www.youtube.com/watch?v=VIs1CxuUrpc

[-Boris-]

I would like to use uncore as umbrella term for everything outside of the CPUcore (or module):
HTr, IMC, L3, XBAR.
Currently it seems that
NB = XBAR + HTr (and in the future in the Llano case probably PCIe)

because everything else is mentioned separately.

Imo it is not important to mention the IMC or HT seperately, every CPU has it nowadays, be it triple channel and QPI for intel or dual channel and Hypertransport for AMD. No use to make a difference here and also no use in mentioning the IMC explicitly but not mentioning Hypertransport by hiding it with the NB term.

AMD should not invent new namimgs, they just should give proper statements, like in case with the AM3 compatibility ;-)

Life would be much easier, haha

But they shouldn't invent new meanings of old names either. System bus interface have never been NB, NB is, and has always been memory controller, and since 1997 people have sometimes included a graphics bus interface. With AMDs latest definition of NB, Core 2 had integrated NB as well.

EDIT: Look at the slider again, they are confusing themselves, they mention two different blocks to contain NB. You have "L3 and NB" and you have "Integrated Northbridge Controller."

[-Boris-]

Well, the board is scheduled for September this year, and Bulldozer is due in ~Q1 2011?

Bulldozer is due 2011, no quarter mentioned yet. Q1 is starting to look very unlikely, they have said something like "release in 2011, but not on December 31st" hinting that it will most likely earlier than late Q4 2011.

[ajaidev]

It maybe that sandy bridge high-end desktop and bulldozer are released in a similar time frame. This would mean off course that llano maybe released before bulldozer , basically it has to because sandy bridge main stream release date closer in hand.

Sandy bridge vs llano will be a blood bath. llano will be slaughtered in cpu power but gpu will be the main attraction people will be left to decide which processor they want.

[STaRGaZeR]

So this is AMD's Hot Chips presentation? Gosh, they didn't say anything new except for Bobcat's L1 and L2 cache sizes as Hans has already said...

[Dresdenboy]

They also provided a more detailed Bobcat architecture diagram.

BTW, regarding AM3 socket:

[Hornet331]

Well they also revealved that each int core only has 2x alus/agus, thats also new.

Hate me for what I am saying, but with this is pretty much given that SB will rape bulldozer in singelthreaded apps. Sure bulldozer will use turbo to offset this handycap, but so does SB.
Multithreading load on the other had will be very interesting, chances are good that amd can win a lot of server share back with this.

What I also wonder how this design will deal with apps that only have limited thread numbers, Lame mp3 encoding comes to mind or many games. For me it seems as long as the thread count is below the physical amount of cores, SB will be the winner and even PII will do better. But if we go higher, Bulldozer will really shows what it is capable off.

So it seems AMD fully aimed at server sapce with this desgin.

[-Boris-]

Well they also revealved that each int core only has 2x alus/agus, thats also new.

Hate me for what I am saying, but with this is pretty much given that SB will rape bulldozer in singelthreaded apps. Sure bulldozer will use turbo to offset this handycap, but so does SB.
Multithreading load on the other had will be very interesting, chances are good that amd can win a lot of server share back with this.

What I also wonder how this design will deal with apps that only have limited thread numbers, Lame mp3 encoding comes to mind or many games. For me it seems as long as the thread count is below the physical amount of cores, SB will be the winner and even PII will do better. But if we go higher Bulldozer will really shows what it is cabable off.

So it seems AMD fully aimed at server sapce with this desgin.

In floating point intensive tasks Bulldozer might perform really well with less than 4 threads as well. Depending on if it will run one thread per module. But since power saving and turbo is per module and not per core it might want to utilize each module fully before turning on the next one.

Four threads would be optimal to run on 4 modules, one thread per module. But power saving and turbo might make the processor to run them on two modules only, thus forcing them to share FPU.

[ajaidev]

Well they also revealved that each int core only has 2x alus/agus, thats also new.

Hate me for what I am saying, but with this is pretty much given that SB will rape bulldozer in singelthreaded apps. Sure bulldozer will use turbo to offset this handycap, but so does SB.
Multithreading load on the other had will be very interesting, chances are good that amd can win a lot of server share back with this.

What I also wonder how this design will deal with apps that only have limited thread numbers, Lame mp3 encoding comes to mind or many games. For me it seems as long as the thread count is below the physical amount of cores, SB will be the winner and even PII will do better. But if we go higher, Bulldozer will really shows what it is capable off.

So it seems AMD fully aimed at server sapce with this desgin.

Yes alus/agus have been taken out but other additions have been made like 4 issue for one. As it is i dont expect PhII to be better in single thread's but sandy bridge is a different story.

Its quite possible that sandy bridge is very good at single threads but then again you dont buy a 8c sany bridge for its single thread performance.I am thinking since power gating is on a module bases most likely so will the turbo. That means that single/dual thread single module will profit from turbo with almost the same speed.

[blindbox]

Like everyone have said, it will not make sense for AMD to name the socket AM3+ if the processor that's going to drop into it won't be compatible with AM3. AM2+ processors are compatible with AM2 mobos. If AM3+ processors are not going to do the same, they would've named it AM4.

[Chumbucket843]

yawn... more boring than i thought. i'll just wait for some interesting info in jssc.

[Opteron146]

So on an AM3 system there are three things that could be called NB, the IMC, the uncore and the PCIe part of the chipset?
Usually the confusion tends to be about the chipset or the IMC, but dragging the uncore to the mix is just unnecessary.
The uncore has nothing to do with traditional NB-functions.

Well the traditional NB had:
FSB Interface, IMC and SB connection.

Now AMD stresses the IMC, so FSB and SB connector are left out.

FSB is now Hypertransport (well at least from the point of view of Multi processing, otherwise it is the Xbar), and the SB connect was back then PCI, nowadays PCIe - seems fine to me.

Noooooooo:
I am listening now to the telephone conference of last week...
On the one hand, one AMD lady speaks of an "electric upgrade", on the other hand, an AMD guy said that:

To clarify on the socket question:

Bulldozer products will not be drop in for AM3; so it will require a different socket, we are calling AM3+, our AM3+ I am sorry AM3 CPUs will be able to - will function in an AM3+ Bulldozer socket, so you can bring your previous CPUs into the AM3 infrastructure, but not the other way round.

Now I guess I know, how the confusions started .. with that guy, because he said AM3 in the end, instead of AM3+.
However in his case - I think it is clear what he wants to say .. he mixed up Am3 and Am3+ before, and he mixed it probably up in the end, too, but I believe he wants to say that it is not compatible

Well seems like AM3+ will be the same like the infamous VRM11 update of S775


Sooo saaad

Let's hope that guy misunderstood something himself - hey AMDs internal flow of information is know to be bad - but honestly I dont think so

[fellix_bg]

Like everyone have said, it will not make sense for AMD to name the socket AM3+ if the processor that's going to drop into it won't be compatible with AM3. AM2+ processors are compatible with AM2 mobos. If AM3+ processors are not going to do the same, they would've named it AM4.

AM2 -- DDR2
AM3 -- DDR3
AM4 -- DDR4 (?)

The Bulldozer socket should still be named AM3 with some revision moniker.

[Opteron146]

So this is AMD's Hot Chips presentation? Gosh, they didn't say anything new except for Bobcat's L1 and L2 cache sizes as Hans has already said...

No, this was just a briefing, all details later today / tomorrow in Asia & Europe

[Hornet331]

Yes alus/agus have been taken out but other additions have been made like 4 issue for one. As it is i dont expect PhII to be better in single thread's but sandy bridge is a different story.

Its quite possible that sandy bridge is very good at single threads but then again you dont buy a 8c sany bridge for its single thread performance.I am thinking since power gating is on a module bases most likely so will the turbo. That means that single/dual thread single module will profit from turbo with almost the same speed.

Yes you dont buy 8c for singelcore performance, but you buy dual, and quads at consumer level.

Consumer app/game loads mostly are only partially threaded, already given some exampels.

I don't say bulldozer will have bad singel thread performance, but its a fact that for 1 thread they have less execution resources then a PII, and with the x6 we already got a x6 that clocks itself to 3,6ghz at singelthreaded loads. They(amd) have to move to a more agressive turbo mode to compensate for the lack of IPC in singelthreaded, partially threaded loads.

edit:
but thats only for the information we have now.

Hope the conference slides give more insight, so everything could change again..

[blindbox]

Well the traditional NB had:
FSB Interface, IMC and SB connection.

Now AMD stresses the IMC, so FSB and SB connector are left out.

FSB is now Hypertransport (well at least from the point of view of Multi processing, otherwise it is the Xbar), and the SB connect was back then PCI, nowadays PCIe - seems fine to me.

Noooooooo:
I am listening now to the telephone conference of last week...
On the one hand, one AMD lady speaks of an "electric upgrade", on the other hand, an AMD guy said that:

Now I guess I know, how the confusions started .. with that guy, because he said AM3 in the end, instead of AM3+.
However in his case - I think it is clear what he wants to say .. he mixed up Am3 and Am3+ before, and he mixed it probably up in the end, too, but I believe he wants to say that it is not compatible

Well seems like AM3+ will be the same like the infamous VRM11 update of S775


Sooo saaad

Let's hope that guy misunderstood something himself - hey AMDs internal flow of information is know to be bad - but honestly I dont think so

That really sucks there. So it's like AM3 and AM2+ then. Upwards compatible, not downwards.

[JF-AMD]

Lostcircuits seems to believe that Bulldozer will be a bobcat with an extra core.

No, way off. They are totally different architectures.

[JF-AMD]

wtf...they didnt even give there presentation yet? how are these even released? i call BS! the conference is pacific time....soo its not happening for awhile!


http://www.hotchips.org/program/conference-day-two/

Those are the press slides and the embargo lifted at midnight.

The hot chips slides are far deeper, but those do not come off embargo until after the presentation.

[informal]

Yes you dont buy 8c for singelcore performance, but you buy dual, and quads at consumer level.

Consumer app/game loads mostly are only partially threaded, already given some exampels.

I don't say bulldozer will have bad singel thread performance, but its a fact that for 1 thread they have less execution resources then a PII, and with the x6 we already got a x6 that clocks itself to 3,6ghz at singelthreaded loads. They(amd) have to move to a more agressive turbo mode to compensate for the lack of IPC in singelthreaded, partially threaded loads.

AT covered the issue with the "issue" in their article here. Basically BD will have higher single thread performance than Deneb class cores.

[JF-AMD]

At least this side has the original AMD slides so that we can separate facts from fantasy.......

http://www.hardocp.com/article/2010/...essors_preview


The only disclosure in the whole document concerns the cache sizes of Bobcat: 32kb L1, 512kb L2
and it contains a typo(?) using kb (kilobit) instead of kB (kiloByte), at least I presume it's a typo....


Regards, Hans

Hans, the hot chips slides are still under embargo. Those are the less detailed press slides.

[JF-AMD]

Here we have the reason. Integrated PCI-Express controller.

EDIT: Well obviously not, but that what techpowerup claims.

Nope. No integrated PCIe. That would not allow us to use the same sockets.

[JF-AMD]

So this is AMD's Hot Chips presentation? Gosh, they didn't say anything new except for Bobcat's L1 and L2 cache sizes as Hans has already said...

No.

[Opteron146]

That really sucks there. So it's like AM3 and AM2+ then. Upwards compatible, not downwards.

No, it is worse, because you could drop in an AM3 CPU into AM2+ mainboards. According to that guy, this is not possible, AM3+ is no drop in for AM3
You only can drop in old AM3 CPUs in new AM3+ boards. But who wants to do that ? Probably only interesting for OEMs which can then use 1 mainboard for the whole Sempron -> Bulldozer line. If there is a company like that ..