You will see a tremendous benefit in memory bandwidth and latency on Intel platforms due to the memory controller have to communicate to the CPU through the FSB.Originally Posted by ShawnTRD
Now on Intel Core i7 and AMD systems tighter timings normally take priority, as the memory controller is on the CPU die (thus behind the FSB.)
Ok here are my settings that are 1h20m prime blended stable:
Maximus Formula Converted to a Rampage Formula
I would like to get DDR2-1141 and tighter MCH latencies....so any advice is greatly appreciated.Code:BIOS: RF0701 Extreme Tweaker Ai Overclock Tuner : Manual OC From CPU Level Up : AUTO CPU Ratio Control : Manual Ratio CMOS Setting : 8 FSB Frequency : 475 DRAM Clock CMD Skew CH1 A1 : AUTO (greyed out? don't remember that..) DRAM Clock CMD Skew CH1 A2 : AUTO (same, greyed out) DRAM Clock CLK Skew CH1 B1 : advance 300ps DRAM Clock CLK Skew CH1 B2 : advance 300ps FSB Strap to North Bridge : Auto PCI-E Frequency: 100 DRAM Frequency: DDR2-950 (would like to run 1141) DRAM Command Rate : 2T DRAM Timing Control: Manual CAS# Latency : 5 RAS# to CAS# Delay : 5 RAS# Precharge : 5 RAS# ActivateTime : 18 (haven't tested lower much) RAS# to RAS# Delay : 3 Row Refresh Cycle Time : 60 (maybe 65 or higher to clock higher?) Write Recovery Time : 6 Read to Precharge Time : 3 Read to Write Delay (S/D) : 8 Write to Read Delay (S) : 3 Write to Read Delay (D) : 5 Read to Read Delay (S) : 4 Read to Read Delay (D) : 6 Write to Write Delay (S) : 4 Write to Write Delay (D) : 6 Write to PRE Delay : 14 Read to PRE Delay : 5 PRE to PRE Delay : 1 ALL PRE to ACT Delay : 6 ALL PRE to REF Delay : 6 DRAM Static Read Control: Enabled (open to suggestions on this one..) Ai Clock Twister : Stronger Transaction Booster : Manual Common Performance Level [9] Pull-In of CHA PH1 Disabled Pull-In of CHA PH2 Disabled Pull-In of CHA PH3 Disabled Pull-In of CHA PH4 Disabled Pull-In of CHA PH5 Disabled Pull-In of CHB PH1 Disabled Pull-In of CHB PH2 Disabled Pull-In of CHB PH3 Disabled Pull-In of CHB PH4 Disabled Pull-In of CHB PH5 Disabled CPU Voltage : 1.52500 (probably can run lower, just for now) CPU PLL Voltage : 1.50 North Bridge Voltage : 1.71 DRAM Voltage : 2.20 FSB Termination Voltage : 1.54 (don't know if I need this much) South Bridge Voltage : 1.1 SB 1.5V: 1.60 Loadline Calibration : Enabled CPU GTL Reference : 0.63X North Bridge GTL Reference : 0.67X DDR2 Channel A REF Voltage : AUTO DDR2 Channel B REF Voltage : AUTO DDR2 Controller REF Voltage : AUTO SB 1.5V Voltage : AUTO
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