Barcelona Opteron 2350(B1) arrived

[gondezz]

Excuse me for this n00b question:

If memory clock is derived from cpu clock divided by some number,
so what is northbridge clock for??

Thanks

[v0dka]

I think it's not really a NB, this is just the IMC speed. On K8 it was always 1:1 with the CPU, apparantly now it's seperate.

This seems interesting to me as on K8 the IMC was suspected to play a major role in the max CPU clockspeed. A typical good K8 had mem revision B1 or BB as you will know, which would get you higher than a good week BW.

[gondezz]

Thanks for reply..
So, IMC speed is 'internal speed' only?
To communicate with the core perhaps?

[kyosen]

I could get 8800GT yesterday

...yes, I can't do 2 CPU operation with long PCIe board

I used 169.01 driver with inf file modified...it looks a bit faster than 167.26.
I tried 2.0G, 2.2G, 2.4G...and in 2.4G case, I tried 3core(1core disabled) and
2core(2core disabled) as emulation of Toliman and Kuma
I also tried on P5K3-D/Kentsfield with mild memory setting...

Results...screenshots are located on my BBS:
http://www.oohashi.jp/c-board/c-boar...ne;no=5231;id=

CPU clock: 3DMark Score / CPU Score

K10(BA) 2.0G=222x9: 9482 / 2999
K10(B1) 2.0G=200x10: 9353 / 2979
K10(B1) 2.2G=220x10: 10148 / 3267
K10(B1) 2.4G=240x10: 10796 / 3560
K10(B1, 3core) 2.4G=240x10: 10420 / 2830
K10(B1, 2core) 2.4G=240x10; 9423 / 1888

Kentsfield 2.4G=267x9: 11901 / 3845
Kentsfield 3.0G=334x9: 12965 / 4792

Quick conclusion from above:
*K10(BA) looks a bit faster than K10(B1), though multiplier aren't same.
*K10 score seems about 10% lower than Kentsfield at same clock.

So, K10 needs more clock!!!

I'll try CineBench10 in next time...
...now very sleeply...it's early morning here in Japan

[Calmatory]

Hmm, so IF the ICM was the limiting factor when overclocking K8, now we can divide ICM speed with K10, will that mean that we can gain intel-like overclocks (+4.5GHz)? :O

[v0dka]

Thanks Kyosen.

Too bad it lags 10% behind Kentsfield now. Maybe Phenom will close the gap to Kentsfield at least.

Thanks for reply..
So, IMC speed is 'internal speed' only?
To communicate with the core perhaps?

Communication is done through the HT bus, which has a seperate speed. The Integrated Memory Controller communicates with the memory (read / write). I invite anyone with more technical background to fill in the details.

Hmm, so IF the ICM was the limiting factor when overclocking K8, now we can divide ICM speed with K10, will that mean that we can gain intel-like overclocks (+4.5GHz)? :O

An interesting theory is it not? But ofcourse there are other factors.

[Sparky]

Thanks Kyosen.

Too bad it lags 10% behind Kentsfield now. Maybe Phenom will close the gap to Kentsfield at least.

According to Perkam, B2 (which IIRC is what Phenom is going to be) is supposed to be much better. At this point I don't know what to believe, though I do hope he is right.

[grunge100]

beardy,

How do you know the barc. proc. was in single channel mode?

[BeardyMan]

It is just BeardyMan having too much hopes about K10.
It was said 1000 times that CPUz displays it as single channel, while it is DUAL channel. It was also confirmed that the system is running in dual channel, comparing the scores of Super Pi with 1 and 2 memory modules. There was a response from Franck of CPUz too, in this thread.

Don't worry, at the end you will come and kneel for me

[grunge100]

smartypants,

K10 is fine, I think its you that has a problem.

[BeardyMan]

Grunge100
OK, go ahead. What problem do you think I have?

have?
are

[LowRun]

Well i noticed Kyson's image says single channel on the AMD rig, perhaps someone chould run single and dual channel on his intel rig and se eteh performance drop...

Dude it's Kyosen not Kyson.

[BeardyMan]

K10(B1) 2.4G=240x10: 10796 / 3560
Kentsfield 2.4G=267x9: 11901 / 3845

It would be interesting to see 267*9 on the AMD system or 240*10 on the intel and then to see how that cpu bench scales

[knightwolf654]

ok i am gonna come out and say it...
SHUT UP
no need for petty arguments.
now mabey i dident see it but is the bored ur running a 1207+? so it can utilize HT3? just curious.

[cky2k6]

yes it would... hard one to predict *concentrating very very hard channelling my clairvoyant powers* oh my god, i got it! no the fsb wouldnt have any damn effect, when the hell has it ever??

[knightwolf654]

i wasent talking the FSB, HT3 is on the die correct? and it would provide direct links to the ram and what not. instead of going through the FSB

[akaBruno]

FSB x the multplier matters. MOBO fsb? Don't mean sh*t.

Things change everyday, though.

[mrcmtl]

FELIX kindly pointed out to me about K10's memory controller
According to AMD's document, BIOS and Kernel　Developer’s Guide,
K10's has 2 DCTs(DCT: Dram ConTroller!?), and it can work different two mode, i.e.,
(1) to behave as a single dual-channel DCT; this is called ganged mode;
(2) to behave as two single-channel DCTs; this is called unganged mode.

My understanding is:
Ganged mode reads or writes with 2 DCTs at the same time.
Unganged mode also can reads with 1 DCT and writes with another 1 DCT at the same time,
if the system requests as so.
Unganged mode is more flexible than ganged mode,
and ganged mode is equal to "conventional" dual channel mode.

)

I dont know how Ganged mode works...if it is a single read/write or two but Unganged mode is two different DCT, there part isn't shared...they both write or read...and just to add, K10 doesnt read/write anymore...it reads until the DCT buffer is out of space and bursts all the awaiting writes to avoid the constant read/write switch delay.

[oldblue]

I'm curious about how the relative clock speed between the L3 and the cores affects the L3 cache latency. If I read this right, some combinations should give lower latency than others.

To support independent clocking and modular design, asynchronous dynamic FIFO buffers are used to communicate between different cores and the northbridge/L3 cache. These FIFOs absorb any global skew or clock rate variation, but the latency for passing through depends on the skew and frequency variance – which is why the L3 cache latency is variable.

[BeardyMan]

K10(B1) 2.4G=240x10: 10796 / 3560
Kentsfield 2.4G=267x9: 11901 / 3845

It would be interesting to see 267*9 on the AMD system or 240*10 on the intel and then to see how that cpu bench scales

Kyosen, in fucntion of this post, when you have the time, no pressure ofcourse. could you test that as well the max fsb? i know the board may be limiting but just to get an glimpse

thx for your efforts

[kyosen]

Kyosen, in fucntion of this post, when you have the time, no pressure ofcourse. could you test that as well the max fsb? i know the board may be limiting but just to get an glimpse

thx for your efforts

I also have interest for max FSB.
This board, KFSN4-DRE, has no HyperTransport multiplier setting in BIOS,
so I should be restricted...
...but now I can change multiplier for each core with CrystalCPUID


Many thanks to Franck, I've inspired and received hints by chatting with you
I think that I should be able to change NB's multiplier, Vcore, Vnb,
within maximum limit which each CPU product has...not yet tested, though.

[BeardyMan]

I also have interest for max FSB.
This board, KFSN4-DRE, has no HyperTransport multiplier setting in BIOS,
so I should be restricted...
...but now I can change multiplier for each core with CrystalCPUID


Many thanks to Franck, I've inspired and received hints by chatting with you
I think that I should be able to change NB's multiplier, Vcore, Vnb,
within maximum limit which each CPU product has...not yet tested, though.

I see, so with this info you would be able to push more out of it?

[MAS]

I think it's not really a NB, this is just the IMC speed. On K8 it was always 1:1 with the CPU, apparantly now it's seperate.

K10's IMC will have the clockspeed equal to cpu clockspeed when installed on old AM2 or 1207 mobo;

and it will have its own clockspeed on AM2+ or 1207+ mobo


as you can see kyosen's mobo adjusted NB speed to 1800 MHz - IMC is slower than cpu. Right decision - server cpu has slow memory, so it doesn't need high-speed IMC (667*2=1333 MHz will be enough)

But in Phenom's case 1800MHz won't be enough - dual-channel ddr2 1066 needs at least 1066*2=2133 MHz, so I expect Phenom's IMC will run >2200 MHz and it's clockspeed will be adjustable - manually or auto

[tictac]

ht link speed multiplier.. require ldt_stop.. imposible to change it in windows.. if this chipset doesnt support ht3. it will hold you back..

[oldblue]

Very good question oldblue. The L3 latency depends of the lowest clocked core which has a dedicated part of the L3. The higher that cores is clocked, the lower the L3 latency is going to be.

Are you sure about that? I wasn't aware that any cores had a dedicated part of the L3 -- I thought it was completely shared.

The way I read the Real World Tech article, the L3 latency should vary from core to core if they're all running at different speeds. The latency for each core seems to be dependent on how that core is clocked relative to the L3, but I'm curious about how this shows up in practice.