IBM published Barcelona SpecCPU results.

[hollo]

So for now, Intel remains in the lead till early Q1 2008.

with penryn coming out, being a few percent faster than c2 clock for clock (in general) as well as higher clockspeeds and even better overclocking (if that's possible), there's no way AMD will be in the lead in q1 2008.

[DoubleZero]

Friday i was lmao with all the FUD that was going around in this forum about K10 when we were at only 3 FRIGGING DAYS from solid numbers... now it's not days it's hours and the FUD remains.

This Red character is making an amazing job, with the watershed of SPEC scores, some of them where SPECint base is higher then peak.

SPEC scores ARE NOT SET IN STONE, did you missed the "miraculous" score improvements Xeon's got in just a few weeks?





What? do you think K10 scores won't go up either? Do you seriously think with the amount of K10 systems that are going to be submitted to SPEC, K10 scores aren't going to rise? How do you know that those IBM scores aren't going to be among the worst that are going to be submitted to SPEC?

Do you want to be fair and look smart? Compare the first Clovertown scores in SPEC to the first K10 scores:

Clovertown -> SPECint2006 12.0 SPECfp2006 10.9

http://www.spec.org/cpu2006/results/...202-00322.html
http://www.spec.org/cpu2006/results/...212-00416.html

K10 -> SPECint2006 11.6 SPECfp2006 11.2

That Clovertown is the best score when it came out, the K10 score we don't know if the best or the worst.

Now some math... comparing the amd leaked slides to the IBM pdf we got this:

K10 1.9ghz -> SPECint_rate2006 83.2 SPECfp_rate2006 73.0

K10 2.0ghz -> SPECint_rate2006 88 SPECfp_rate2006 77.2

K10 performance raises around 5,5% with only 100mhz.

Base in the latest SPEC scores submitted by Intel, c2d only gets a 9,5% jump in performance with 333mhz, where K10 with 300mhz will get something like 16,5 % boost, so or K10 IPC is higher or those IBM scores are low.

[NickS]

Cache has a totally different effect on Intels cpus than it does on AMD ones. There is virtually no noticable difference in performance between 256, 512 and 1mb per core cache on A64s. where the difference between 2mb and 4mb is quite noticeable on C2D.


Im interested in seeing how the power functions of the new processors does. Im selling my laptop off since alot of the features look very nice for notebooks.

People say this but theres quite the difference in games with 512K and 1024K L2 cache & K8's

[onewingedangel]

K10 performance raises around 5,5% with only 100mhz.

2.0/1.9= 1.0526.....

so a 5.3% increase in core clock results in an equivilent increase in performance, colour me suprised

When core clocks are so low of course the percentage gain is going to be great for small increases in clock, as core speeds increase each 100mhz results in a lower percentage improvement.

100 to 200mhz results in 100% improvement
1900 to 2000 just over 5%
2900 to 3000 just under 3.5%

Its only when I/O is a bottleneck that you'll see less than ideal scaling, and at low speeds theres certainly not going to be a bottleneck. If we were talking about the highest end parts then the fsb would probably provides some problems with scaling, but going from 1.33 to 2.66 to 3ghz sees a similar increase, so IO doesn't seem to be a bottleneck.

[v_rr]

Barcelona is Native quad-core.
Teoricaly it will scale lot better with higher clocks then C2D.

Remember cooaler Cinebench?
AMD scaled more 10% then C2D at 2.0Ghz passing from single to multi-tread.

Also there are the articles that speak that Barcelona will show it´s power only with 2.5Ghz.
Tomorrow I wan´t to see a 2.5 to 2.8Ghz K10 overclocked to see the true K10 power.

[dave_graham]

guys, again, there are significant performance deltas between the release stepping of the core and the B0/B1 steppings.

without much more information than that, you just need to keep your panties in check.

dave

[Hornet331]

guys, again, there are significant performance deltas between the release stepping of the core and the B0/B1 steppings.

without much more information than that, you just need to keep your panties in check.

dave

so ibm also uses b0/b1 stepping ?

[DoubleZero]

2.0/1.9= 1.0526.....

so a 5.3% increase in core clock results in an equivilent increase in performance, colour me suprised

I guess i got caught by the dumb rumours that K10 scaling wouldn't be linear...

[JumpingJack]

2.0/1.9= 1.0526.....

so a 5.3% increase in core clock results in an equivilent increase in performance, colour me suprised

[JumpingJack]

Base in the latest SPEC scores submitted by Intel, c2d only gets a 9,5% jump in performance with 333mhz, where K10 with 300mhz will get something like 16,5 % boost, so or K10 IPC is higher or those IBM scores are low.

What was the starting clock where you calculated that 9.5%?? % improvements without a common base will throw you into the wrong conclusion.... for example.

1.9 to 2.0 GHz improvement gives 5% roughly, but 2.5 to 2.6 Ghz is 4%...

if you are calculating from 2.66 to 3.00 gigherzt this is roughly a 12% so 9.5% is not horrid scaling but does demonstrate some BW limiting performance effects.

[DoubleZero]

if you are calculating from 2.66 to 3.00 gigherzt this is roughly a 12% so 9.5% is not horrid scaling but does demonstrate some BW limiting performance effects.

Does 2.00 to 2.33 make it worse?

[dave_graham]

so ibm also uses b0/b1 stepping ?

depends on when the benches were run.

dave

[pawl]

4 years since the k8 - and all theyv doen is put 4 cores on a chip.

all those new designers + design centres and the ipc increases 3% on the core. what have they been designing?

they must have known internally that the ipc sucked - hence no leaks. otherwise they would have leaked like crazy like intel with the core.

hope im wrong - cause if im right the amd is going down.

[gallag]

depends on when the benches were run.

dave

Dave. you have been pretty optimistic about k10 as of late, you have certainly been one of the more vocal members in defending any sign of weakness from k10 blaming it on steeping etc and pretty much hinting that k10 is going to wipe the floor with intel and I have been believing you but I must admit that it is a stretch not to think IBM has it right, No?

I suppose it is only a few hours till we find out if you are on the level

[Fatal Error]

It has begun....

[dave_graham]

Dave. you have been pretty optimistic about k10 as of late, you have certainly been one of the more vocal members in defending any sign of weakness from k10 blaming it on steeping etc and pretty much hinting that k10 is going to wipe the floor with intel and I have been believing you but I must admit that it is a stretch not to think IBM has it right, No?

I suppose it is only a few hours till we find out if you are on the level

of course i've been vocal.

here's what i've been vocal about:

a.) people assuming that Cinebench 10 and SuperPi results as tested by coolater on a B0/B1 stepping processor are the presumptive indicator of performance for an entire range of processors.

b.) people making snap-assumptions that benchmarks that are published by Tier One vendors are the gospel even when, as we've seen with Dell and IBM, there are SIGNIFICANT VARIANCES IN PERFORMANCE.

c.) people using B0/B1 stepping performance claims to downplay AMD's ability to produce silicon that falls in line with the performance claims they've made in the past.

do I have a lot of experience on this platform? yes.
do I have a lot of background information covered under NDA from AMD and Tyan? yes

i don't drink the Kool-aid. I simply look for the people that do and try to correct it.

seriously. anything i've posted as of late has been to correct significantly incorrect perceptions on Barcelona and it's process to market.

if Intel would actually give me the time of day, I might be inclined to do the same there, but, i don't have the time, money, or anti-AMD attitude that they desire.

*shrug*

clear as mud to me.

in questioning these IBM results, i'm simply providing input that if IBM used B1 stepping processors (versus the BA/B2 stepping processors that will be present at launch), there's going to be significant notable impact on "scores" unless the proper workarounds are implemented.

waiting until tomorrow is somewhat laughable since outside of a very few talented individuals, i'm expecting a load of poorly done "thanks for the free chips, AMD...you rock!" reviews that have ABSOLUTELY nothing to do with the capabilities of the platform.

EDIT: at least i'm intelligent in my responses versus some of these asshat Intel/AMD fanboi's who believe without reason. again, knowledge is power.

dave

[Motiv]

EDIT: at least i'm intelligent in my responses versus some of these asshat Intel/AMD fanboi's who believe without reason. again, knowledge is power.

dave

I take it you'll be using the newer steppings for your review?

Just out of interest, is the final silicon significantly faster or are the boards hindering its performance?

[JumpingJack]

4 years since the k8 - and all theyv doen is put 4 cores on a chip.

all those new designers + design centres and the ipc increases 3% on the core. what have they been designing?

they must have known internally that the ipc sucked - hence no leaks. otherwise they would have leaked like crazy like intel with the core.

hope im wrong - cause if im right the amd is going down.

From the scant data we currently have, oodles more tomorrow --- my opinion is that AMD looked at the K8 core from a heavy FPU perspective, along with increasing the FPU/SSE to 128 bit, and where they thought they would bottleneck put significant efforts into improving BW.... about 1/2 of the core features were targeted to BW improvements.

As such I would call K10 a success because we are seeing huge improvements in FPU multithreaded performance. Also, AMD designs to the server space first then works that into desktop. As such, a server design for desktop works to an extent.... but DT is not as dependent on BW as is server workloads.

What I think we will ultimately see is great improvements over K8 in the server space, and a competitive product against the competition... on DT there will be case of isolated gains, but on average the improvement IPC wise on CPU bound workloads may be less than expected as a result of the focus on server/throughput.

[STaRGaZeR]

Don´t worry, here in Europe just 2 minutes to Sept.10th

I want to see some real numbers, good or bad. All this speculation sucks.

[Motiv]

Don´t worry, here in Europe just 2 minutes to Sept.10th

I want to see some real numbers, good or bad. All this speculation sucks.

it'll be around 1-2 in the afternoon till the NDA is lifted in Europe.

[STaRGaZeR]

And some time before all the reviews are done and published. So don´t worry anymore.

[Morais]

confused

[JPeitzman]

excited ...but also confused


Can't wait though, got to go start another pot .....

[terrace215]

of course i've been vocal.



in questioning these IBM results, i'm simply providing input that if IBM used B1 stepping processors (versus the BA/B2 stepping processors that will be present at launch), there's going to be significant notable impact on "scores" unless the proper workarounds are implemented.

IBM says the results are current as of Sep 10, 2007. Sounds like they would be using the production stepping, if they bothered to put out a whitepaper on it, and why would IBM submit pre-prod stepping results to SPEC??? That just doesn't seem at all likely.

Notice the lame system availability date as well.

Barc is a paper launch from the big OEMs.

From the pdf:

Results are current as of September 10, 2007. The scores have been submitted to SPEC for review and will be posted on their Web site upon successful completion of the review. View all
published results at www.spec.org.
(1) Planned availability for the x3455 model using the AMD Opteron Model 2347 processor
(1.9GHz, 512KB L2 cache per core) is November 16, 2007.

[PetNorth]

More IBM benchs (LS-DYNA benchmark) with Barcelona 1.9ghz

What's this bench?

"LS-DYNA, developed by the Livermore Software Technology Corporation, is a general-purpose transient dynamic finite element program capable of simulating complex real world problems. It is optimized for shared and distributed memory Unix®, Linux®, and Microsoft® Windows® platforms. LS-DYNA is being used by automobile, aerospace, manufacturing and bioengineering companies. LS-DYNA is heavily used in automobile crash simulation."


Result:

The x3455 server achieved an elapsed time of 31,526 seconds, which is better than the 32,578 seconds of elapsed time achieved by a single-node 8-core blade system using the Quad-Core Intel® Xeon® X5355 processor at 2.66GHz.

So, two Barcelona (8 cores) at 1.9ghz, about 3% faster than two Clovertown (8 cores) at 2.66ghz (with 40% less clock than Clover).

ftp://ftp.software.ibm.com/eserver/b...yna_091007.pdf