AMD new E6 revision replaces E3 one's

[Ratax]

" Model numbers 3800+, 3500+, 3200+ and 3000+ in socket 939 only will be affected by the new revision change from E3 to E6.

The E6 revision is pin to pin compatible with the current E3 revision, and will function in existing platforms based on 939 pin AMD Athlon(tm) 64 processors, but a new BIOS will be required to recognize the new CPU ID (Current CPU ID will change from 00020FC0h to 00020FC2h).

This new revision is expected to start shipping from July 15th 2005 and the marking of the affected model numbers will change as shown below:

MODEL NUMBER PREVIOUS PIB REF NEW PIB REF
3800+ ADA3800BPBOX ADA3800BWBOX
3500+ ADA3500BPBOX ADA3500BWBOX
3200+ ADA3200BPBOX ADA3200BWBOX
3000+ ADA3000BPBOX ADA3000BWBOX
"
Source: AMD email.

There will be new E6 revisions in socket754 models too.
The mail doesn't says about changes in this E6 revision.

[OC Detective]

Does that not mean that if a mobo supports the new E6 single core then it must also support the E6 dual core too which by extrapolation means that any mobo that supports E3 will support E6 dual core?
Your source is named as "AMD email" - I assume then it is 100% legit.

[frostedflakes]

So wait, E6 is the dual core revision, correct?

Why are the single-core Venice going to be using these? Is AMD planning to sell X2s with a failed core as Venice (similar to the 512KB Clawhammers on S754 and S939)?

[hitmanx2]

will they be better overclockers?

[Fairydust]

Even more important, what is a fitting nickname for the Toledos?

Going from San Diego's Sandy to Toly? No that doesn't sound good, so Tod Toledo, Ted Toledo, hmm yeah Teds are nice people :P let's call it Ted(d)y.

[OC Detective]

So wait, E6 is the dual core revision, correct?

Why are the single-core Venice going to be using these? Is AMD planning to sell X2s with a failed core as Venice (similar to the 512KB Clawhammers on S754 and S939)?

I guess that is possible, streamlines the process optimises output and the core size is similar to a 130nm Newcastle anyway.

[SIOUX]

Even more important, what is a fitting nickname for the Toledos?

Going from San Diego's Sandy to Toly? No that doesn't sound good, so Tod Toledo, Ted Toledo, hmm yeah Teds are nice people :P let's call it Ted(d)y.

Mad man

[EvilWhiteDragon]

Even more important, what is a fitting nickname for the Toledos?

Going from San Diego's Sandy to Toly? No that doesn't sound good, so Tod Toledo, Ted Toledo, hmm yeah Teds are nice people :P let's call it Ted(d)y.

I think we should call them Do's, Toledo's

[Gorod]

will they be better overclockers?

I wonder the same thing , it is time to sell E3's and prepare for E6 ?

[Fairydust]

I think we should call them Do's, Toledo's

No way, this breaks the unwritten rule "Thou shalt use at least the first letter of the word which is to be abbreviated."

[STEvil]

wonder if you could enable the second core if its there..

[dimasdw]

MODEL NUMBER PREVIOUS PIB REF NEW PIB REF
3800+ ADA3800BPBOX ADA3800BWBOX
3500+ ADA3500BPBOX ADA3500BWBOX
3200+ ADA3200BPBOX ADA3200BWBOX
3000+ ADA3000BPBOX ADA3000BWBOX

BP is venice and what is BW ?
maybe we can call Toledo, TODO or TOLE

[dimasdw]

wonder if you could enable the second core if its there..

enable the second core with pencil trick

[Davos]

so why have they brought this out?? will it overclock better??

[STEvil]

BP is E3
BW is E6

for those who didnt catch on.

[mad mikee]

Sorry just woke up and could resist since someone already came up w/ rev6 = todo

[s7e9h3n]

BP is E3
BW is E6

for those who didnt catch on.

Then what's BV? BTW, I think TULLY would be appropriate

[bugeyes]

probably failed dualcore - e3 + e3 = e6

Wrong... e3 + e3 = 2e3

[dimasdw]

@s7e9h3n

BV is Manchester 512 kb L2 Cache
and CD is Toledo 1 Mb L2 Cache


@STEvil

so BP is venice with rev E3 and BW is venice with rev E6 right ?

[Davos]

Wrong... e3 + e3 = 2e3 hmm but e3 is the same as 3e

e3 can also be written as 3e

3e + 3e = 6e

but if it was e³ + e³ then it would be 2e³

soz

[mongoled]

Wrong... e3 + e3 = 2e3

Nice, had me chuckling there

[Crosis]

I would like to how they will be o/cin' according to Venice...

[eva2000]

@s7e9h3n
acording to your screenshot BV is Toledo
and CD is denmark (X2 with 1 Mb L2 Cache)
http://www.watch.impress.co.jp/akiba...mage/nx2d2.jpg

That yours ?

[s7e9h3n]

@s7e9h3n
acording to your screenshot BV is Toledo
and CD is denmark (X2 with 1 Mb L2 Cache)


@STEvil

so BP is venice with rev E3 and BW is venice with rev E6 right ?

Gee thanks , I know it may be hard to believe, but you can't always trust cpu-z's ID's. This is the exact same cpu as above (I sent it to OPB):

[situman]

so E6 revision chips are still dual channel? Its just a failed dual core?