The different memtest bandwidth between fx55 and venice

[Onepagebook]

I remember some has mentioned before, why my FX55 DDR600 above , 2.5-3-3-6 bandwidth got so low bandwidth. Now with venice core , you guys can easily see this and understnad.
Apparently, memtest86+ 1.55 can't recognize this new core of AMD CPU.

FX55 doing DDR600 2.5-3-3-6



Venice 3500+ doing DDR610 2.5-3-3-6

[esdee]

OPB on a FX53 that i tested i noticed much lower bandwidth than newcastles/winchesters, now i see the same thing on fx55s

the IMC on almost every winchester and many newcastles (newcastles behaved better tho) seemed to crap out over 3500MB/s affecting their stabilty inside windows @ high clock freqs
Can you test how the venice core behaves under Win. (stability @ lets say 3700MB/s)

that would be interesting imo

thanks

[Bluebeard]

no answer on this OPB?

[Zanr Zij]

OPB... Bandwidth show on memtest belong to other setting in Dram configuration ( DFI ) 2.5-3-3-6 don't say ev'rything . Ex : if u relax Trc ( and other ) from 7 to 9 or 12, memtest will show lower bandwidth... But I thinks venice's mem controller better than my Winnie

[mad mikee]

Based on a few diff chip types and a few years of painful experience (present pain included). You can have:
1. 512K cache and great BW
2. 1M cache and noticably less BW

This seems to stretch back to old 754 days when I could get 2000mb/sec on my 3000+ NC w/ crappy settings @ 250 x 9 but 1750 max @ good settings on CH CG chips @ same speeds.

Like the balance better on the 512k chips, never getting another 1M cache chip again.
(SPI scores seem about the same though )

[esdee]

Based on a few diff chip types and a few years of painful experience (present pain included). You can have:
1. 512K cache and great BW
2. 1M cache and noticably less BW

This seems to stretch back to old 754 days when I could get 2000mb/sec on my 3000+ NC w/ crappy settings @ 250 x 9 but 1750 max @ good settings on CH CG chips @ same speeds.

Like the balance better on the 512k chips, never getting another 1M cache chip again.
(SPI scores seem about the same though )

higher l2 cache may yield higher latency on the IMC ... i'd stick to the 1mb chips tho