How to set up GTL Ref Values for 45nm & 65nm

[CryptiK]

For a good explanation of what GTL Ref voltages are and do, go here:

http://www.thetechrepository.com/showthread.php?t=87

I will simply explain how to set them for your particular CPU and motherboard. They are very important for quad core cpu's, but also affect the stability of dual core cpu's.

A GTL Ref voltage is derived from the Vtt (vFSB) voltage. The GTL voltage is a certain percentage of the Vtt so to set it you use a multiplier (eg: 0.667x) which means the resulting voltage is 0.667x (66.7% of) the Vtt voltage.

For 45nm CPU's, on boards where you just set the multiplier, you should begin with the 0.635x multiplier for each core, and for 65nm CPU's, you begin with the 0.667x setting for each core. From there you tweak as necessary to find the optimum sweet spot for you cpu & FSB.

Some new boards (like Maximus II Formula) use a different method for setting the GTL Ref voltages. They do not simply have a multiplier, the multiplier remains fixed and you enter a 'Y value' that modifies the resultant voltage.

If you have a 45nm cpu, you are aiming for the voltage given by the 0.635x multiplier, so to work out what to put for the the 0.667x GTL Ref (Y) values (it will be a negative number to make the resulting voltage the same as the 0.635x GTL Ref voltage), use the following eqn, but substitute the Vtt you use, in place of the example Vtt.

In the examples given, I have rounded off to 3 decimal places throughout for simplicity.

For me, Vtt = 1.14v

Equation:

Vtt x 0.667 + Y = Vtt x 0.635

1.14v x 0.667 + Y = 1.14v x 0.635
0.760v + Y = 0.724v
Y = 0.724v - 0.760v
Y = -0.036v
Y = -36 mv

So to verify it:
1.14v x 0.635 = 0.724v
1.14v x 0.667 = 0.760v

0.760v - 0.036v = 0.724v

or an easier, non algebraic alternative:

1.14v x 0.635 = 0.724v
1.14v x 0.667 = 0.760v
0.724v - 0.760v = -0.036v
= -36mv

Round up to the nearest selectable bios value, in Maximus II Formula bios this is -40mv

So now you set the 0.667x 'Y value' to -40mv

You have now made the 0.667x GTL voltage as close as possible to the 0.635x GTL voltage.

If you have a 65nm cpu, you are aiming for the voltage given by the 0.667x multiplier, so to work out what to put for the the 0.635x GTL Ref (Y) values (it will be a positive number to make the resulting voltage the same as the 0.667x GTL Ref voltage), use the following eqn, but substitute the Vtt you use, in place of the example Vtt.

For me, Vtt = 1.14v

Equation:

Vtt x 0.667 = Vtt x 0.635 + Y

1.14v x 0.667 = 1.14v x 0.635 + Y
0.760v = 0.724v + Y
Y = 0.760v - 0.724v
Y = 0.036V
Y = 36 mv

So to verify it:
1.14v x 0.667 = 0.760v
1.14v x 0.635 = 0.724v

0.724v + 0.036v = 0.760v

or an easier, non algebraic alternative:

1.14v x 0.667 = 0.760v
1.14v x 0.635 = 0.724v
0.760v - 0.724v = 0.036v
= 36mv

Round up to the nearest selectable bios value, in Maximus II Formula bios this is +40mv

So now you set the 0.635x 'Y value' to +40mv

You have now made the 0.635x GTL voltage as close as possible to the 0.667x GTL voltage.

**EDIT**

Naming and meaning of the CPU gtl ref's, and land pin assignment names (Kindly provided by Mikeyakame):

CPU GTL Reference (0/2 Lane0/Lane2)
GTL Reference Data Strobe Input Buffer Middle/End Landing Pins 0 & 2. (GTLREF0/GTLREF2)

CPU GTL Reference (1/3 Lane1/Lane3)
GTL Reference Address Strobe Input Buffer Middle/End Landing Pins 1 & 3 ( GTLREF1/GTLREF3 )

For quad-core multi-die chips:
Middle Landing Pins (GTLREF0/1) act as input buffer for DIE0, End Landing Pins ( GTLREF2/3 ) act as input buffer for DIE1.

For dual core single-die chips:
Middle Landing Pin (GTLREF0/1) acts as input buffer for DIE0, End Landing Pin (GTLREF2/3) uncertain if used. Either unused and terminated to open drain Vtt or used as reference for middle pins as margin of error.

Things to note concerning adjustment:
Address strobe Pins (GTLREF1/3) will generally tolerate small variance with respect to reference voltage accuracy, and should in most cases be setup a little lower with respect to Data strobe Reference multiplier or voltage.
Why?
Probably the same reason as any other reference or input voltage for clock strobes, signal resonance or cross talking.

Data strobe pins (GTLREF0/2) will not tolerate being out by more than 0.5-1% below nominal, but will tolerate slightly more above nominal. Keep set values above Address Strobe GTL multiplier/voltage offset.
Why?
Works better in almost all situations, don't know why until I get a chance to monitor on a logic analyzer.
By How Much?
Varies according to FSB base clock, higher the FSB BCLK the smaller the difference will probably need to be at least with respect to the Diff Amplitude driving the clock.

Also not that when you are adjusting the GTL Refs with a board that using a fixed multiplier and a modifier (eg: +/- in mv) the resultant Vref will be slightly different for the data strobe lanes and the address strobe lanes, as shown by this example (Kindly provided by Seban):

Calculations made for a Vtt = 1.365v

GTL Ref 0 = +50mv = 0.9336025v
GTL Ref 1 = +10mv = 0.9381305v
GTL Ref 2 = +50mv
GTL Ref 3 = +10mv

GTL Ref 0 = +30mv = 0.9136025v
GTL Ref 1 = -10mv = 0.9181305v
GTL Ref 2 = +30mv
GTL Ref 3 = -10mv

As you can see, the resulting Vrefs are not quite equal, but they are close enough for the sake of GTL Ref adjustment. The aim is not to have the Vrefs all exactly the same, but to find the GTL Ref settings that give you the most stability.

**EDIT 2**

Attached to this post is a spreadsheet kindly made by Seban, allowing easy calculation of GTL Refs required, as a starting point fo your tweaking. Here is his description of it:

I got little present for every one for new year .

It is simple Excel file which is counting GTLs and NB GTL as well as new Multiplier for you and few other minor values for given Vtt. It is nothing special but saves time and allows to tweak GTLs without asking for help and getting too much into it.

How to use it:

First type in desired / currently used vtt voltage as in your bios (or rather the way it looks loaded in Everest for example - but bios one is also working fine)

Secondly put some correction numbers and watch how GTL values are changing (Max and Min values of GTL for given VTT are also shown there).

The goal is to figure out which GTL works best for you for one VTT - in most cases the same GTLs voltages will work for different VTTs or very similar ones (or sometimes not ). So when we switch Vtt we would need to adjust GTLrefs to values which will give same or close to same GTLs as working previous ones for different vtt.

Anyway have fun using it, I created it to make my life easier and it does the job.

PS. There are 2 sets of values to compare between different VTT.
PS2. This calculator is made for MF2 board but will work with all boards that got correction number in equation (like +40 or - 20 and so on).

[Xello]

Originally Posted by CryptiK

For 45nm CPU's, on boards where you just set the multiplier, you should begin with the 0.635x multiplier for each core

I read this elsewhere too, but people i've talked to seem to generally be going for 0.67x for the QX9650 / Q9450.

Nice write up

[Philly_Boy]

my QX9650 is liking -50mv on cores 0 & 2....that's even a bit lower than the 0.635 that's recommended. If I let it at 0.67 then it isn't as stable.

[Polizei]

Originally Posted by CryptiK

For me, Vtt = 1.14v

Equation:

Vtt x 0.667 - Y = Vtt x 0.635

1.14v x 0.667 - Y = 1.14v x 0.635
0.760v - Y = 0.724v
Y = 0.724v - 0.760v
Y = -0.036v
Y = -36 mv

Your algebra is wrong there in the first part. You lost the negative sign with the Y... it should be +36mV, not negative.

[Singh400]

Thanks for trying to explain, but after reading it through 10 times, I'm still left confused

I will keep at it...

[CryptiK]

Originally Posted by Polizei

Your algebra is wrong there in the first part. You lost the negative sign with the Y... it should be +36mV, not negative.

I have way oversimplified this for ease of explanation. The answer is in fact -36mv for the 0.667x Y value, but I was debating about how to show that. I thought the way I wrote it showed more clearly what had to be done rather than be mathematically perfect.

This is correct mathematically, but I thought having '+Y' in both equations may confuse people:

Equation:

Vtt x 0.667 + Y = Vtt x 0.635

1.14v x 0.667 + Y = 1.14v x 0.635
0.760v + Y = 0.724v
Y = 0.724v - 0.760v
Y = -0.036v
Y = -36 mv

I have changed it now in the first post.

[Polizei]

Something still isn't right.

At first, you were subtracting a negative, which made it positive. Now you are adding a negative, which is negative.

Maybe I'm just going nuts.

EDIT:

Yours:
1.14v x 0.667 - Y = 1.14v x 0.635
0.760v - Y = 0.724v
Y = 0.724v - 0.760v
Y = -0.036v
Y = -36 mv

Mine:
1.14v x 0.667 - Y = 1.14v x 0.635
0.760v - Y = 0.742v
- Y = 0.742v - 0.760v
Y = -0.742v + 0.760 [multiple both sides by -1 to remove the negative sign infront of Y]
Y = 36mv


When you subtracted the 0.760 from both sides, you seem to have dropped the negative sign infront of the Y. As long as it's corrected in the first post, fine by me... just making sure we are both on the same page. I hope it doesn't seem like I'm trolling... I just want to make sure I understand this Vtt stuff too because P45 is confusing the hell out of me. I went from 975x to P45... big jump.

[Cable_Tie_Guy]

@ CryptiK

It is very easy to see that you are wrong...
Your formula is:

Vtt x 0.667 = Vtt x 0.635 + Y

Can't you see that there isn't a solution for that equation, when Y=0?
And I can set it to 0 if I want to on my board.

[CryptiK]

No, you are mathematically correct in your statement, I did drop the minus in front of the Y. What I meant is, it should have been expressed as

Vtt x 0.667 + Y = Vtt x 0.635

1.14v x 0.667 + Y = 1.14v x 0.635
0.760v + Y = 0.724v
Y = 0.724v - 0.760v
Y = -0.036v
Y = -36 mv

But I expressed it deliberately incorrectly as

Vtt x 0.667 - Y = Vtt x 0.635

1.14v x 0.667 - Y = 1.14v x 0.635
0.760v - Y = 0.724v
Y = 0.724v - 0.760v
Y = -0.036v
Y = -36 mv

I did it like that initially in an attempt to make it clear that when setting up for a 45nm cpu, you must put a negative number (eg: -40mv) for the 0.667x multiplier Y value. However I think it would be better to express it as I have now, which is using a '+Y' in each of the examples, and it is now mathematically correct. Thanks for the feedback, it was clear what I was doing & why in my mind, but it's good to know that it would be better to just express it mathematically correctly rather than the way I had it initially.

Here's the corrected example with full working:

Vtt x 0.667 + Y = Vtt x 0.635

1.14v x 0.667 + Y = 1.14v x 0.635
0.760v + Y = 0.724v

subtract 0.760 from both sides of the equation

Y = 0.724v - 0.760v

Y = -0.036v
Y = -36 mv

Make sense now?

[CryptiK]

Originally Posted by Cable_Tie_Guy

@ CryptiK

It is very easy to see that you are wrong...
Your formula is:

Vtt x 0.667 = Vtt x 0.635 + Y

Can't you see that there isn't a solution for that equation, when Y=0?
And I can set it to 0 if I want to on my board.

Of course there is no solution to the equation when Y = 0, but that is not the point of this. We must solve the equation for Y. What I am doing is showing you how to find the appropriate value for Y to adjust the voltage produced by 0.667 x Vtt to yield as close to the voltage produced by 0.635 x Vtt, how to adjust the voltage produced by 0.635 x Vtt to yield as close to the voltage produced by 0.667 x Vtt.

On your board if you put 0 for Y, you are not adjusting it at all, you have just the multiplier x Vtt, eg: 0.635 x Vtt + 0 = 0.635 x Vtt

[firebane]

All fine and dandy but not all boards have a CPU VTT.

My Biostar Tpower I45 doesn't have it unless I'm blind and missed it somewhere in the crazy amount of bios settings.

[Shiranui Gen-An]

Originally Posted by firebane

All fine and dandy but not all boards have a CPU VTT.

My Biostar Tpower I45 doesn't have it unless I'm blind and missed it somewhere in the crazy amount of bios settings.

It's there, labeled FSB Voltage: http://enthusiast.hardocp.com/image....8xOF9sLmdpZg==

[picnic]

Originally Posted by Singh400

Thanks for trying to explain, but after reading it through 10 times, I'm still left confused

I will keep at it...

I'm with you on this

Anyone want to dumb it down a bit more?

[andressergio]

Thanks Cryptik

I use .61ref on CPU to my Q6600 on my P35 board and .67red to the NB, seem to go up well on that values, achieved stable what it's on my sig

Cheers mate
Sergio

[Big Lar]

So in reality if I am getting this correctly, the Equation is for the Newer boards like the Formula correct? I think thats why my brain is twisted in a knot now.

Larry

[emoners]

thanks for the write up man...hope it would be as easier now.

[CryptiK]

Originally Posted by Big Lar

So in reality if I am getting this correctly, the Equation is for the Newer boards like the Formula correct? I think thats why my brain is twisted in a knot now.

Larry

Yes the equation is what some boards like the M2F use, rather than just the multipliers. If you just have the multipliers, start with 0.635x for 45nm and 0.667x for 65nm, it's as simple as that.

It's only on the boards where they give you the Y value to modify that you need to use the equation to work out the appropriate Y value.

[mikeyakame]

Intel spec specifies all 45Nm and 65Nm desktop chips XE and non-XE use the same GTLREF[3:0] multiplier values. It's Motherboard manufacturers that don't follow the specs possibly due to design?

This is taken from the processor specification documentation for the 45Nm QX9770.

[CryptiK]

Interesting, as I could find no such reference to AGTL+ bus voltage definition in the e7000/8000 data sheet.

[Singh400]

So to simplifier you take your FSB Termination Voltage (VTT) and multiple it by whatever increments you have for GTLs, right?

IE:

45nm:
VTT x GTL increment = GTL Refs

1.22 x 0.635 = 0.7747

Or have I got that completely wrong?

[Xello]

Originally Posted by Philly_Boy

my QX9650 is liking -50mv on cores 0 & 2....that's even a bit lower than the 0.635 that's recommended. If I let it at 0.67 then it isn't as stable.

Blackops X48 seems to love 0.67x, at least it's working for us over at the quantum force section. ( http://www.xtremesystems.org/forums/...d.php?t=201022 )

I guess it must depend on the mobo, which i thought was wrong... But i can't think of anything else.

[mskvorc1]

I'm running my EVGA 750i FTW with pencil mod. I have 1.31825V in BIOS & 1.304V under load and idle in Windows. This voltage is enough for 3,825 GHz (8,5x450). So with adjusting GTL Ref values I should be able to hit higher clocks at lower voltage, right? Mine FSB VTT is 1.20V in BIOS and 1.18V in Windows (at least Everest say's so...).

[mikeyakame]

Originally Posted by mskvorc1

I'm running my EVGA 750i FTW with pencil mod. I have 1.31825V in BIOS & 1.304V under load and idle in Windows. This voltage is enough for 3,825 GHz (8,5x450). So with adjusting GTL Ref values I should be able to hit higher clocks at lower voltage, right? Mine FSB VTT is 1.20V in BIOS and 1.18V in Windows (at least Everest say's so...).

Yes provided you raise VTT you should be able to. it's dependant on the VCore voltage, FSB frequency and VTT voltage. GTL reference voltages vary for different input and output voltages. The curve is not linear by far. What ratio or extra millivolts might work great for one vCore and one VTT might be out of range for another. It's alot of trial and error mostly. Look at that graph on the Techrepository article for FSB frequency vs GTL reference voltage and make sure you understand clearly what is happening. It will save you many hassles believe me. GTL reference voltage adjustment has the capacity to fine tune vCore and FSB frequency, along with NB voltage, but also has the same capacity to send your system haywire from bounce or jitter.

[mikeyakame]

Originally Posted by Philly_Boy

my QX9650 is liking -50mv on cores 0 & 2....that's even a bit lower than the 0.635 that's recommended. If I let it at 0.67 then it isn't as stable.

It not cores 0 & 2. It has nothing at all to do with cores. 0 & 2 means GTLREF[0] (GTLREF_ADD_MID) and GTLREF[2] (GTLREF_ADD_END) which are address bus clocking low/high reference land pins. 1 & 3 means GTLREF[1] (GTLREF_DATA_MID) and GTLREF[3] (GTLREF_DATA_END) which are data bus clocking low/high reference land pins. They are for each die respectively. 0 & 1 feed die0 and 2 & 3 feed die1. It's possible I have them back to front, but I'm pretty sure this is the correct order.

[mikeyakame]

Originally Posted by CryptiK

Interesting, as I could find no such reference to AGTL+ bus voltage definition in the e7000/8000 data sheet.

Aye we are all here to help each other. I don't think any other spec datasheet lists the GTLREF voltage specs besides the QX9000 one. I haven't seen it in any other datasheet at least.