Wrote a small article on chipset strap etc

[Tony]

May help you guys, I posted it on the OCZ support forums.

http://www.bleedinedge.com/forum/showthread.php?t=22297

I will add how it effects overclocking etc next. For now it explains ram ratio's, strap and chipset overclocking.

T

[informal]

Nice work Tony,just what we need

[Deathspawner]

Great reading material over morning coffee. Thanks Tony!

[farksy]

Nice stuff !!!

Now i know what the 'straps' mean ... =D

[Tony]

Well I see lots of theories with many people still moving from A64 to Conroe and being unsure, I thought it best to explain just how it works

What a lot don't get is the internal latency change from 1066 to 1333strap is huge, and has a massive effect on memory performance. The sooner motherboard manufacturers give us control of the chipset in the same way we can control the ram and CPU the better, having it locked to the CPU as it is causes all sorts of overclocking issues...LOL

[farksy]

Well I see lots of theories with many people still moving from A64 to Conroe and being unsure, I thought it best to explain just how it works

What a lot don't get is the internal latency change from 1066 to 1333strap is huge, and has a massive effect on memory performance. The sooner motherboard manufacturers give us control of the chipset in the same way we can control the ram and CPU the better, having it locked to the CPU as it is causes all sorts of overclocking issues...LOL

Hmmm ic ... But i tot i read somewhere that the 1066 strap did perform better than the 1333 strap in some cases, don't know how true that will be.

So the strap depends on the default speed of the chip ? Then how do they change the strap used by the board ?

[The Stilt]

Nice article but it doesn´t say anything about clock generator straps.

Basically the pll can be the one which craps out first, not the chipset.
Thats why certain boards (like "rev. E") have jumpers or transistors which change the pll start frequency (PLL strap).

I believe that Asus is using this kind of feature in P5W DH.
The board clearly changes strap when it is being booted with certain (267, 334, 401FSB) frequency.
Since the performance doesn´t vary between the straps and the fsb overclockability increases it is more likely that the change is done by pll strap and not nb strap.

[ivo0613]

Thanks, Tony.

[Makubex_GB]

Very nice, thanks.

[Tony]

Nice article but it doesn´t say anything about clock generator straps.

Basically the pll can be the one which craps out first, not the chipset.
Thats why certain boards (like "rev. E") have jumpers or transistors which change the pll start frequency (PLL strap).

I believe that Asus is using this kind of feature in P5W DH.
The board clearly changes strap when it is being booted with certain (267, 334, 401FSB) frequency.
Since the performance doesn´t vary between the straps and the fsb overclockability increases it is more likely that the change is done by pll strap and not nb strap.

I try to keep things ultra simple here, i do actually say the clockgen is reset once you up a strap ratio.

BSEL pins tell the chipset/clockgen what base strap/fsb to use...you then push up from there.

The info is there, just not slapping you in the face, i have to keep it easy for those less in the know than us

I will follow it up with overclcoking the memory soon and possibly explain more in depth then also.

For those who think the upclock ratio is not working on badaxe im pretty certain it is, its just the chipset has an ultra slack latency set and performance is crap. What we need to do is sift thru the whitepapers(the ones Intel keeps hidden) and see what latency tweaks are available to quicken things up a little

[Haltech]

Well Tony, your help is appreciated, especially to those of us who are new to the Intel platform and DDR2 clocks.

[cadaveca]

Just like doing the L12 mod on socket A then, but by bios?

[tzitzos]

thx tony

[fhpchris]

Great reading material during class Tony, thanks

[afireinside]

Thanks Tony I'll give it a read tonight. Should help a lot of people

[don_vercetti]

Looking forward to the memory half of your article...that's where i'm currently having big trouble with my Allendale setup.

[bugeyes]

Thats a very helpful article, especialy for some one like me, as conroe will be my first intel based rig. Look forward to reading the rest of it.
regards mike.

[jrw]

I now feel almost certain that the "independent memory overclocking" thing on the RD600 is just what Conroe needs.

Nice explaining Tony. Even I could understand it

[SMa]

I now feel almost certain that the "independent memory overclocking" thing on the RD600 is just what Conroe needs.

Nice explaining Tony. Even I could understand it

Altough it will probably still be better to keep FSB and RAM in a certain ratio.

Nice article,
but where do you get all that information from?

[Tony]

Altough it will probably still be better to keep FSB and RAM in a certain ratio.

Nice article,
but where do you get all that information from?

Years overclocking memory, it is all i do and how i got this job with OCZ. I study what makes memory clock on a given platform and find the best way to get everything working as sweet as it can be.

I cut my teath on Northwood CPU's on 845 and SIS chipsets, in all i had 21 CPU's and over 60 pairs of BH5 looking for the ultimate combo of CPU and memory, in the end i just used mobile northwoods modified to run the 800 strap by breaking off BSEL1 pin on the CPU.
100%+ overclocks etc on air and BH5 at 260fsb on 845 chipsets etc was what i started with and I kept true to learning each chipset as Intel released it.

[drunkenmaster]

so wait, i get all of that no problem. but can you help me out on one bit, its the PLL strap that kicks in at certain fsb, so with the 401fsb start, what exactly does that mean. in that case if you boot at 401fsb it will lock that at 1066 strap with normal timings so no loss in performance. would that mean the northbridge is running a different divider and the normal (stock) speed despite the cpu being at a much higher divider? if thats the case then there should be a lot of head room for fsb from 401fsb up if the northbridge is essentially at stock at this point? or if not, what does the pll strap do differently?

cheers

[SMa]

Do all Intel chipsets work the same?
Like my 955X on the Asus P5WD2 Pr?

[Tony]

All Intel chipsets work the same, starting from 845 up. The clockgens are based on the chipset straps so work the same way pretty much

[Tony]

so wait, i get all of that no problem. but can you help me out on one bit, its the PLL strap that kicks in at certain fsb, so with the 401fsb start, what exactly does that mean. in that case if you boot at 401fsb it will lock that at 1066 strap with normal timings so no loss in performance. would that mean the northbridge is running a different divider and the normal (stock) speed despite the cpu being at a much higher divider? if thats the case then there should be a lot of head room for fsb from 401fsb up if the northbridge is essentially at stock at this point? or if not, what does the pll strap do differently?

cheers

When you force a strap change will BSEL signals, you reset the clcokgen and the chipset to a default clock. The clockgen may now have a 1066fsb start point and the NB is on a 1066 strap and have all the memory ratios allowed by this strap and a base clock frequency.

its all about control....but you need I/O chips and bios code to do it, which most boards at this time do not have

[_damien_]

@ Tony:

There are a couple of things I've been wondering about, and I would appreciate your input

Asus pretty much were the pioneers of this, they found the chipset register which enabled “Performance Acceleration technology” or “PAT” on the 875 chipset and went looking thru the white papers for the 865 chipset to see if any settings/registers had the same effect. What they found was that the 865 chipset forced to the 533 strap (133fsb for us mortals) set the same register as the 875 chipset with PAT enabled. They also found at lower strap values Intel forced a latency change on the chipset that improved memory performance with the memory being at a lower clock peed.

Is this the same as what Abit did with their IS7-series (which has 865 chipset and unofficial PAT-support) ?

Does this mean that 533 strap in a sense enables PAT on any mobo of that generation, despite what the Intel tech doc says?

The MCH supports Performance Acceleration Technology (PAT). PAT is only available when the MCH is set at FSB 800 MHz and DDR 400 MHz mode. PAT enables lower latency paths from the FSB to system memory. This enables increased system performance for the 875P chipset system.

And I don't understand how the command rate is accessible in certain BIOSes, when the controller is reported to not support 1T at all.

Ever since Intel launched the 865 chipset over clocking the chipset has been a major factor in enhancing Intel motherboard performance. We all know that Intel force the CPC on their chipsets to 2T , a way to claw back some of the performance is to clock the chipset higher, which in theory reduces its internal latency and improves memory performance.

I know there is no official support for 1T, but in the BIOS of my Abit IC7-G, there is a CPC-option, and enabling it affects stability the way 1T command rate actually would. (Haven't been able to compare performance, because it fails to boot at 1T with two sticks populated). This makes me wonder what Abit did, Would it be possible to implement a BIOS-feature that really affects the setup time of the memory controller?