here some feedback from user

JimmyPage @PCPerspective Forums
tested all kinds of settings, ended up at 1-3-4-3-3-4-4 read top to bottom. Provides greatest bandwidth (about 40MB/s more than 5-4-6-3-3-5-6, about 15MB/s more that 1-3-3-3-3-3-4) and doesn't seem to limit my FSB at all.

No errors at any speed up to the limit in Memtest.

This is done with 2x256 CH-5 in DC, btw

oh ya here some reference for Alpha Timing

Code:
Alpha Timing Parameters

T = latency/timing in number of clocks
DOE = ???
RRD = Row Active to Row Active Delay
W2P = Write to Precharge
W2R = Write to Read
REXT = ???
R2P = Read to Precharge
R2W = Read to Write
if u have any other memory timing register plz let me know..