Dresdenboys' blog: AMD Bulldozer - Patent based research

[Oliverda]

bulldozer on am3+ this doesnt make sense..

Why?

[haylui]

Why?

maybe DDR4 would be introduced that time. So, til then new socket to cater new RAM type and build in GPU altogether (even DDR4 never comes out and we are stuck at DDR3)

DDR4 rumoured to launch in 2012

source: http://xtreview.com/addcomment-id-61...r-in-2012.html

[Sn0wm@n]

maybe DDR4 would be introduced that time. So, til then new socket to cater new RAM type and build in GPU altogether (even DDR4 never comes out and we are stuck at DDR3)

DDR4 rumoured to launch in 2012

source: http://xtreview.com/addcomment-id-61...r-in-2012.html

doubt that we will see an amd ddr4 board on ddr4 launch... amd will probably wait till ddr4 has matured a bit

like they did with ddr3 and not sure about ddr2 on how it happened since i just got introduced to oc'ing

[Manicdan]

doubt that we will see an amd ddr4 board on ddr4 launch... amd will probably wait till ddr4 has matured a bit

like they did with ddr3 and not sure about ddr2 on how it happened since i just got introduced to oc'ing

i dont know how hard it would be for them to make a quick ddr4 memory controller and chipset.

even if the performance is very little. people who are extreme will happily pay 200$ more for a cpu that supports ddr4, just so they can say they have it. "AMD extreme edition". 5% stronger, 50% more expensive.

[hlopek]

Bulldozer will be made up in a similar way a new arc. but a base has to be there like Pentium was for the Nehalem, maybe bulldozer will be based on Am386 or K6, both are very good arc's.

Am386 & K6 were really good at their time and better solution than Intel's previous generation CPUs that were design to compete with. Let them rest in peace. I'd say it would be extremely wrong if AMD would now reject some 15yrs of K7 development and good ooo architecture in favor of some io CPUs
If AMD could develop ooo engine by itself out of nothing in the K6-2/K6-3 time they wouldn't need reassembly Alpha to produce first real ooo chip four years after Intel's Pentium Pro. So it would be lose lose situation in times when AMD looses it's competitiveness in high-end desktop/workstation market segment.

Bulldozer won't have the same underlying Kx architecture and will be design around totally different concept(in order to achieve maximum throughput both in int and fp workloads).The only thing that may resemble the Kx will be HyperTransport in the uncore part of the chip and FP/SSE in the core part.The latter(SSE units) will in reality still be 2x + faster than in the K10.5 due to AVX 256bit support and possibly other improvements.

Yes but that's still OneCore that has 2x 128b wide ALU and 256b FPU that they now call X2? It's pure propaganda to claim it X8 when trully capable octa core Sandy Bridge CPU came out.With same AVX capability but inside real core not shared over Unified-X2-Core

Could you explain that HT connections in UnCore part, so does that mean that L3 and every "X2-core" itself will be connected by some HT like bus? And not with truly 64 byte wide bus as it has been rule for all L1/L2 caches from first Athlons with on die L2 cache. L3 also use same 64 byte width bus.

doubt that we will see an amd ddr4 board on ddr4 launch... amd will probably wait till ddr4 has matured a bit

like they did with ddr3 and not sure about ddr2 on how it happened since i just got introduced to oc'ing

You could be wrong about that DDR4 support cause they did support DDR3 already in 2007 with Barcelona/Agena just they didn't want to pust it out cause of DDR3 prices, availability and possibly because TLB bug With DDr2 suport is even more weird story cause they done it 2006 cause they didn't desperatly needed bandwidth as Intel NetBurst architecture and their QBP did.

In the time of SDRAM/DDR SDRAM transtion AMD was firt that was introduced DDR chipset for their Athlon (Thunderbird/Spitfire) chips for socket A.

So they could done it once again with DDR4 if they need it for any stupidest reason as marketing bragging rights Ever since K7 their CPUs need as low latency as they could get and every new DDR iteration increases latency further. So yo do the math why they always stalling with newer emory type adoption

Maybe they'll use DDR3-DDR4 mixup for some Fusion chips cause graphics always has need for more bandwith. Or they even might introduce their Fermi/Larabee GPGPU sharing same "future AMD LGA" socket as CPU. So there's even a slight chance that they adopt first DDR4 for a reason

[Sn0wm@n]

http://blogs.amd.com/work/tag/magny-cours/


i doubt that if the server is adopting a new socket for the 12 cores etc... that the 8 cores non mcm chip will get to keep am3+ but i could be wrong

c32/g34


btw dresdenboy what you have done on the patent research is amazing!

[Nedjo]

latest GloFo's roadmap from whom is easy to pinpoint sample timeframe of Ll(el)iano:



source: http://www.pcper.com/article.php?aid=814

[informal]

Just in from web cast:


Bulldozer won't have classic "core" but something AMD calls modules !
Bobcat is alive,sub 1W operation,super low power but has 90% of mainstream performance of today's mainstream CPUs! Fully modular and ready for APU implementation, has OoO abilities,2-way execution,very high performance and IMO looks like one BD "module"

Now on to BD: confirmed CMT design! More in a minute!
In : Int units are shared(2x2way execution),1 256b wide FPU.My God,DDboy hit the nail on the head,he is 99% correct in his speculation.

more: highly advance clock gating,shutting down individual modules for best perf./watt ratio,Turbo like APM functionality.
AMD states all of this is going to be a game changer.

[Mechromancer]

Just in from web cast:


Bulldozer won't have classic "core" but something AMD calls modules !
Bobcat is alive,sub 1W operation,super low power but has 90% of mainstream performance of today's mainstream CPUs! Fully modular and ready for APU implementation, has OoO abilities,2-way execution,very high performance and IMO looks like one BD "module"

Now on to BD: confirmed CMT design! More in a minute!
In : Int units are shared(2x2way execution),1 256b wide FPU.My God,DDboy hit the nail on the head,he is 99% correct in his speculation.

more: highly advance clock gating,shutting down individual modules for best perf./watt ratio,Turbo like APM functionality.
AMD states all of this is going to be a game changer.

ALL HAIL DRESDENBOY!

Hyperthreading = PWNT

[informal]

^^ in the above quote there is a chance it's 2x 4-way int clusters instead of DDboy's speculation about 2x2-way since AMD lists 4 "pipes" in the BD module diagram. But i have no idea if these are simple or complex instructions mentioned there. In patents there is a mention of possible total of 8(eight!) instructions being executed in parallel (due to ability to execute additional 4 fastpath ones in the same clock cycle)

[Mechromancer]

^^ in the above quote there is a chance it's 2x 4-way int clusters instead of DDboy's speculation about 2x2-way since AMD lists 4 "pipes" in the BD module diagram. But i have no idea if these are simple or complex instructions mentioned there. In patents there is a mention of possible total of 8(eight!) instructions being executed in parallel (due to ability to execute additional 4 fastpath ones in the same clock cycle)

Once again I say:

AMD =

[Chumbucket843]

Hyperthreading = PWNT

CMT = paper

[haylui]

CMT = paper

AMD didn't choose multi-threading like Intel did for their Pentium 4 in the Athlon 64 and their realized that it is a mistake. So they won't do this again!!!

[Particle]

CMT = paper

I don't think that's accurate. Since CMT isn't something they're likely to just tack on at the end and AMD is likely to be experimenting with pieces on silicon at this point, I think it's rather more likely that it isn't just some neat concept paper. At the very least, its physical implementation has probably been designed.

[Smartidiot89]

[rcofell]

Page 16 for the block diagram in the PDF

[Nedjo]

Guys! I suggest that mods create dedicated "AMD Analyst day 2009" thread and move all of the latest post from here to this new thread? What do you say?

[w0mbat]

Guys! I suggest that mods create dedicated "AMD Analyst day 2009" thread and move all of the latest post from here to this new thread? What do you say?

[Nedjo]

thanks!

due to urgency of being on time before all threads go on flame I've created this thread: http://www.xtremesystems.org/forums/...d.php?t=238702

come and give us yours 2 cents

[informal]

Bobcat core(more precise word:module) diagram:


edit: Smartidiot beat me to it,so i will put Bobcat diagram instead of BD one .

[FlanK3r]

i watch at it, its good !

[FlanK3r]

now im waiting at server and clients platforms

yes, its here clients platform presentation

[informal]

I just checked again and it is 4 way execution indeed with 2x2way clusters within one module(CPU core) and these two are sharing one wide(256b) SIMD unit.The front end for 4x4way would be way to much complex and expensive ,at least for this generation of products.But still is an option for future iterations of this (previously) unseen design approach. Fastpath comment still stands(even more so now) since 4 fastpath above 4 complex instructions give us precisely total of 8 instructions in one cycle,as dresdenboy found out in his research.
What is amazing is level of detail he "guessed",he has been correct in almost every part of his speculations.I remember Savantu and his bashing against ddboy's blog,how it is just pure wishfull thinking and imagination,how semi companies patent useless stuff all the time etc. Looks like he is this year's honorable bunnysuit winner .

CMT = paper

Yes for now,but it is mini-revolution in 2011 . The approach is novel and needs to be applauded since it's a brave move from AMD.
CMT was all paper for years now,there is academic research papers but not 1 firm ever even presented a possible design solution. The design is much more potent than half-threading(SMT in intel's way of doing things),since resource sharing is done much better in hardware(via common front end and separate int execution units that can share data and one shared dual threaded SIMD unit-a best of both worlds approach). How will it work in practice we'll have to wait and see,but AMD stated that one small bobcat core(based on smae bulldozer) is at the 90% level of today's mainstream performance ,all with that very low power draw .

edit: let's not forget Hans de Vries and his chip-architect website which detailed this very same approach 7 years ago(IIRC). This was the original Hammer design,not the sledgehammer aka K8 which AMD launched back in 2003(not to say K8 wasn't good,quite opposite). Back in those days Hans presented a possible future core from AMD that resembles exactly what dredenboy depicted in his diagrams and what AMD presented today .

[Mechromancer]

I just checked again and it is 4 way execution indeed with 2x2way clusters within one module(CPU core) and these two are sharing one wide(256b) SIMD unit.The front end for 4x4way would be way to much complex and expensive ,at least for this generation of products.But still is an option for future iterations of this (previously) unseen design approach. Fastpath comment still stands(even more so now) since 4 fastpath above 4 complex instructions give us precisely total of 8 instructions in one cycle,as dresdenboy found out in his research.
What is amazing is level of detail he "guessed",he has been correct in almost every part of his speculations.I remember Savantu and his bashing against ddboy's blog,how it is just pure wishfull thinking and imagination,how semi companies patent useless stuff all the time etc. Looks like he is this year's honorable bunnysuit winner .

Yes for now,but it is mini-revolution in 2011 . The approach is novel and needs to be applauded since it's a brave move from AMD.
CMT was all paper for ears now,there is academic research papers but not 1 firm ever even presented a possible design solution. The design is much more potent than half-threading(SMT in intel's way of doing things),since resource sharing is done much better in hardware(via common front end and separate int execution units that can share data and one shared dual threaded SIMD unit-a best of both worlds approach). How will it work in practice we'll have to wait and see,but AMD stated that one small bobcat core(based on smae bulldozer) is at the 90% level of today's mainstream performance ,all with that very low power draw .

CMT = paper

An we'll soon have a runner up.

[madcho]

if i understand well, 2 core shares 8 int pipelines. So in a dual core with a dual threaded apply you have up to 8 int/clock.
And on same processor, with a monothread apply you can have up to 8 int/clock, because it's shared on 2 cores.
On a Quad, with a multithreaded bench with 4 thread you can have up to 16int/clock, and with only 2 thread you can have up 16int/clock if the "good cores" are used. If only one thread 8/clock.

Phenom II is based on athlon with only 3/clock/core.

The performance increase could be amazing if they increase L3 to fetch that monster.