Quote Originally Posted by EMC2
Just to put this to bed, so to speak...

CAS latency as normally thought of is the latency from CAS going low till when the first data is available during a READ from memory, measured in clock cycles. Side-note is that the memory chips themselves must also support and be programmed for whatever CAS latency is set for READ accesses Here are scope pics showing what you really get for various CAS latencies (READs). The memory was run at 100Mhz (1:2 Divider) to make it easier to see the time delta from CAS to the first data (indicated by the rising edge of DQS after the Read Preamble). Regarding the quality of the signals... this was a quick and dirty session using the "hang-a-wire-instrumentation" method... but you still "get the picture" :
Nuff said

Peace
Wow thanks for posting that, cool to see how the RAM really works.