AMD new E6 revision replaces E3 one's

**panumas05** · 06-09-2005, 09:03 AM

E6 in Dual core.

http://www.xbitlabs.com/articles/cpu...on64-x2_3.html

But new BW is disable Dual core and disable cache ?

**metro.cl** · 06-09-2005, 10:01 AM

weird anyone can tell more???

**setyotomo** · 06-09-2005, 10:17 AM

@s7e9v3n : 9476 PC Marks

**[XC] leviathan18** · 06-09-2005, 10:57 AM

i dont think disable core disable cache is more likely to be faulty core or cache

**~~terrace215~~** · 06-09-2005, 11:03 AM

Originally Posted by dimasdw

@s7e9h3n
acording to your screenshot BV is Toledo

and CD is denmark (X2 with 1 Mb L2 Cache)

@STEvil

so BP is venice with rev E3 and BW is venice with rev E6 right ?

BV is used for Manchester (2 x 512K L2)
CD is used for Toledo (2 x 1MB L2)

And, BTW, clearly, AMD is not going to use 2 x 1MB L2 die for Venice (1 x 512K L2) parts.

So, more than 1 die (cache size, etc) can use the same "E6" stepping.

For a while I thought AMD was using the #s just to differentiate dies, with E3, E4 and E6 all being the same "E" stepping, but if this email is correct, that is clearly not the case.

**_Eduard_** · 06-09-2005, 11:43 AM

I can't wait for E6 sempr0ns

**Quanticles** · 06-09-2005, 12:10 PM

Originally Posted by Davos

e3 can also be written as 3e

3e + 3e = 6e

but if it was eÂ³ + eÂ³ then it would be 2eÂ³

soz

e3 is a variable name though, you cant have it start with a number =P

**s7e9h3n** · 06-09-2005, 01:21 PM

Originally Posted by setyotomo

@s7e9v3n : 9476 PC Marks

That's not my work, it's OPB's with the cpu he got from me...

**dimasdw** · 06-09-2005, 03:07 PM

Originally Posted by eva2000

That yours ?

no,thats picture from a Hardware website

**dimasdw** · 06-09-2005, 03:31 PM

Originally Posted by terrace215

BV is used for Manchester (2 x 512K L2)
CD is used for Toledo (2 x 1MB L2)

oh sory I am Wrong,your right ....
I forgot where i read about denmark and Toledo

Link
<translate with http://world.altavista.com/babelfish/tr>

**Borgschulze** · 06-09-2005, 05:56 PM

Originally Posted by s7e9h3n

Then what's BV? BTW, I think TULLY would be appropriate

Hey, how about we call them...
TOLEDO!

**CNCL** · 06-09-2005, 09:17 PM

Wait, I am lost. Is the new E6 venice/SD core?

**OC Detective** · 06-09-2005, 10:03 PM

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.

**TMM** · 06-09-2005, 10:04 PM

Could just be a minor core revision...

like the Clawhammer C0 and CG...

Maybe the Venices (if E6 = Venice) will finally have a decent Mem controller

**Fairydust** · 06-10-2005, 12:42 AM

Originally Posted by OC Detective

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.

Correct me if I am wrong, but according to AMD, the 1 Mb version is the E6 and the 512 Kb is the E4

**Lithan** · 06-10-2005, 12:53 AM

Originally Posted by dimasdw

BP is venice and what is BW ?
maybe we can call Toledo, TODO or TOLE

Bout time someone got it right.

Let my provlaimation go across the land!
They wil be known as Todos!

**Fairydust** · 06-10-2005, 01:05 AM

But teddies are cute and fluffy. Todos are mean and smelly. so we got Todos, Tully and Teddy now?

**AgentVX** · 06-10-2005, 01:17 AM

Originally Posted by OC Detective

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.

Then we should call the dual core one Man United and the single core one will be Man City

(English football joke)

**shuRe** · 06-10-2005, 01:22 AM

winchester = winny

san diego = sandy

toledo = toley, or TROLLEY

**The Coolest** · 06-10-2005, 08:04 AM

The AMD K8 0.13Âµm Hammers were SH7-B3, SH7-C0, SH7-CG, there was also a DH7-CG.
the SH7s were Sledgehammers and Clawhammers, the DH7 was a NewCastle.
The first gen of AMD's K8 0.09Âµm Hammers were DH8-D0 and SH8-D0.
SH = 1MB
DH = 512KB
7 = 0.13Âµm
8 = 0.09Âµm
9 = 0.09Âµm Dual Core
Its very confusing lately as AMD isn't saying what type any of the E stepping hammers are.
But I'm guessing that the new E6 sempron is going to be a DH8-E6, the current Dual cores are *probably* DH9-E4 for DC 2x512KB and SH9-E6 for 1x1MB

**dinos22** · 06-10-2005, 04:20 PM

E6 we're there dude

...i know man......winnie, sandy, teddy....WTF....

Originally Posted by LOE

does every amd core need to have a :banana::banana::banana:got name?

**s7e9h3n** · 06-10-2005, 04:27 PM

Originally Posted by The Coolest

The AMD K8 0.13Âµm Hammers were SH7-B3, SH7-C0, SH7-CG, there was also a DH7-CG.
the SH7s were Sledgehammers and Clawhammers, the DH7 was a NewCastle.
The first gen of AMD's K8 0.09Âµm Hammers were DH8-D0 and SH8-D0.
SH = 1MB
DH = 512KB
7 = 0.13Âµm
8 = 0.09Âµm
9 = 0.09Âµm Dual Core
Its very confusing lately as AMD isn't saying what type any of the E stepping hammers are.
But I'm guessing that the new E6 sempron is going to be a DH8-E6, the current Dual cores are *probably* DH9-E4 for DC 2x512KB and SH9-E6 for 1x1MB

**The Coolest** · 06-10-2005, 04:38 PM

i'm in contact with CPUz author, and I'm not sure whether its a DH or SH yet, but it sure is a 9-E4. Actually I think I gave him the info on the codes for these chips..

**ArcTan** · 06-10-2005, 04:53 PM

Originally Posted by dinos22

E6 we're there dude

...i know man......winnie, sandy, teddy....WTF....

winnie and sandy sound like girl names
thats what it should be

**Cooper** · 06-10-2005, 05:02 PM

Haven`t you guys noticed that Sempron E6 has the same CPUID as Sempron 64 ???

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