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Thread: Problem=DDR500, Solution=JDEC

  1. #1
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    Problem=DDR500, Solution=JDEC

    As you might recall boys and girls, the whole DDR SDRAM industry went through hell to agree on a JDEC DDR400 standard (for the longest time only DDR266 and DDR333 were available, with the initial DDR200 quickly fading away).

    When all the dust had cleared we had readily available PC3200 3-4-4-8 sticks on the market... whopptie doo.
    Thankfully, Winbond came along, and suddenly there were low latency PC3200 and even PC3500. Folks like OCZ even expanded into PC3700 territory. Surely this would be a sign that a new JDEC standard will come? No.. but legend of BH5 lives on.

    So whats my point? 2 years ago we had the technology to make DDR SDRAM @ 250Mhz with 2-2-5-1 timings (mind you with 3.3-3.4V). Surely we can do much better now. I know that 99% of market is dedicated to making chips as cheap as possible... but, if engineers at Samsung, Micron, Infineon, Hynix, etc.. put their minds together, and spared no expense, I'm sure they could develop better than BH5. Perhaps this memory would be more expensive, but I'm sure most overclockers wouldn't mind since they have lived with this fact of life for ages.

    Considering that Intel is on the DDR2 bandwagon, who better to spearhead theDDR500 movement than AMD (how obvious). The HT is already at 250Mhz, and mem controler doesnt seem to have limits.. so no probs there. Wouldn't it be great seeing Intel DDR2 667 face off against AMD DDR500, or dare I say even DDR600 (low latency)... and not just for overclockers, but I'm talking about readily available mass produced standard AMD platform.


    thats my $0.02


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  2. #2
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    Don't you think if they could have done it already they would have? DDR has been out for years now and they've been looking for faster and better all along. There seems to be a huge barrier between 250MHz 2-2-2-5 and 300MHz 2-2-2-5 (on BH-5 at least).

    The closest I can think of to what you're saying is what OCZ did with their EB series. It could do ~280MHz 3-2-2-X @ 3.3-3.4V on good sticks, and sometimes even higher speeds. Most people stuck with BH-5, though.

    I see what you're saying Deimos, and I agree that I'd love to see some DDR600 action at 2-2-2-5 for the average guy, but it isn't going to happen soon, if ever. DDR2 research seems to have taken centre stage. :/
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  3. #3
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    Quote Originally Posted by mcnbns
    Don't you think if they could have done it already they would have? DDR has been out for years now and they've been looking for faster and better all along. There seems to be a huge barrier between 250MHz 2-2-2-5 and 300MHz 2-2-2-5 (on BH-5 at least).

    The closest I can think of to what you're saying is what OCZ did with their EB series. It could do ~280MHz 3-2-2-X @ 3.3-3.4V on good sticks, and sometimes even higher speeds. Most people stuck with BH-5, though.

    I see what you're saying Deimos, and I agree that I'd love to see some DDR600 action at 2-2-2-5 for the average guy, but it isn't going to happen soon, if ever. DDR2 research seems to have taken centre stage. :/
    My point was to make a DDR500 JDEC specification. DDR600 would be a side effect, of better DDR500 chips (ie binning). But, since we have DDR600 TCCD, with a bit more engineering, I dont see reason why you cant make that a standard, and integrate it into the AMD platform.

    One again, the combination of DDR600 and low timings would be icing on the cake as result of tight timing DDR500 standard and/or loose timing DDR600 standard.

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  4. #4
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    Quote Originally Posted by ***Deimos***
    My point was to make a DDR500 JDEC specification. DDR600 would be a side effect, of better DDR500 chips (ie binning). But, since we have DDR600 TCCD, with a bit more engineering, I dont see reason why you cant make that a standard, and integrate it into the AMD platform.

    One again, the combination of DDR600 and low timings would be icing on the cake as result of tight timing DDR500 standard and/or loose timing DDR600 standard.
    We need to slap anyone in the JEDEC stuff....

    They need to look at how this stuff is doing... were at a 50% clockspeed increase, and only 400mhz is JEDEC...

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