Discuss some DQS

[Rabbi_NZ]

OK, I have some questions...

1) Am I right in thinking that DQS alters where each data bit is sampled? So by changing its value we can get it to sample at the most stable part of the data bits... where they are most likely to have stabilised at either 1 or 0?

2) If what I said above is right, I guess selecting Increase & Value would mean the sampling is done "later" in each bit... so some kind of a delay is implemented in the AMD Memcontroller? Am I close?

3) So... If I AM on the right track I understand how we can "Increase" DQS, but what I don't get is how we can "Decrease" it?
Are the options "Increase"/"Decrease" relative to the MIDDLE of each data bit?
EG, the BIOS auto calculates the middle of each data bit based on the frequency, and tries to allocate a DQS value that will fall there... then if we select "Decrease" the value (I'm guessing a Timer/Counter preload value or something similar) will be reduced... moving the sampling closer to the previous clock edge?

If I am rambling please give me a virtual beeetch slap hehehe

[EMC2]

Hi bro

OK, I have some questions...

1) Am I right in thinking that DQS alters where each data bit is sampled? So by changing its value we can get it to sample at the most stable part of the data bits... where they are most likely to have stabilised at either 1 or 0?

The edge of DQS is used to sample the data. By changing how far DQS is phase shifted by the DLL, you can achieve optimal alignment.

2) If what I said above is right, I guess selecting Increase & Value would mean the sampling is done "later" in each bit... so some kind of a delay is implemented in the AMD Memcontroller? Am I close?

See comment to #1 above... the DLL is what creates the phase shift... it is not a pure delay. Through the use of the DLL the DQS signal can be moved so that it occurs later or earlier. And yes, the DLL is in the memory controller resident in the CPU. (note, there is also one in the memory chip used to align the clock signals, but it is a self-adjusting DLL that you can't program).

3) So... If I AM on the right track I understand how we can "Increase" DQS, but what I don't get is how we can "Decrease" it? Are the options "Increase"/"Decrease" relative to the MIDDLE of each data bit?

Yes, relative to the middle... although the DQS signal as it leaves the memory chip is actually aligned with the "edge" of the data "window".

EG, the BIOS auto calculates the middle of each data bit based on the frequency, and tries to allocate a DQS value that will fall there... then if we select "Decrease" the value (I'm guessing a Timer/Counter preload value or something similar) will be reduced... moving the sampling closer to the previous clock edge?

No, there isn't any "autocalulcation" done by the BIOS. However, I would bet that Oskar is trying to tune the newer BIOS's RAM tables with some pretty good "default" values based on the type of RAM used. Note that when you set the DQS skew value, you are overiding the default value the BIOS sets it to.

The "starting point" (a zero value for skew) is basically a phase shift of 90 degrees. IF the DQS (data strobe) and DQ (data) signals arrived without any distortion, difference in transition time, etc., etc. then they would be optimally aligned with a value of 0. The adjustment is needed because in the real world, there are signal distortions, unequal delay paths, unequal loading, mismatches between termination values, etc.

If I am rambling please give me a virtual beeetch slap hehehe

As you wish

hehehehehehe Not that I would ever ramble

Sometimes a pic is worth a thousand words... try this one out bro