amd dual core preview

[saaya]

Again this comes down to cores.

FX 51, 53, 55, Opteron, Newcastle: Clawhammer (called Sledgehammer in 940 package)
Winchester 512k: Winchester.

I'm not actually sure if all newcastles use the clawhammer core or if they are also built on their own (my guess is they are built on their own and failed clawhammers become newcastle, with the newcastle core filling in when there arent enough failed claws)..

New San Diego and Venice cores only add to the mix..


Someone needs to upload pics of each core, I thought you had a thread up with pics from each (except winchester of course) a year or so ago saaya but I could have been mistaken...

yepp, and i had a pic of a winchester core even back then already
newcastle is a different core with only 512kb l2 cache physically, the failed clawhammer chips with only 512kb l2 cache enabled are actually still labeled clawhammer in cpu-z and not newcastle. afaik almost all 512kb l2 cache a64s are newcastle cores and there are only few with clwhammer cores with half the cache disabled. i havent seen a clawhammer with half the cache disabled for months tbh...

and there are more cores, theres also an a64 core wich only has 256kb l2 cache phsyically made in 90nm wich is used for the mobile semprons and also for some desktop semprons.
and some of them even have half their cache disabled so they only have 128kb l2 cache. they still perform pretty good for the original celeron like sized l2 cache and they are super cheap (70€ here in germany and prices are still going down)

EMC2, thx for all those infos
so amd left themselves quite a lot of options of to add to the current technology as well... really nice n clean design... good engineering

and about intel, well they told me that smithfield is hooked up to the system just like a single core cpu, while with pressler each cpu will be hooked up to the plattform like the current single core cpus.
but this means (or thats what i understand from it) that smithfield MUST have some sort of an x-switch like amd, but for some reason they are making a step backwards by removing the switch and giving each cpu its own interface for pressler.
the added bandwidth is nice, but wouldnt it make more sence to keep the switch and make the bus faster or wider? because they will HAVE to go for a switch anyways sooner or later if they keep adding more cores.

or is it the same to have two independant small buses or have one shared bus wich is two times as wide?
i thougt that one bus of double the width would be more efficient in case both cpus request the same data for example...

and about future cores, amd told me the next move will be 4 cores on one die, i guess in 65nm. they said going for one die is better because the cpus can be hooked up internally and you save pins that way, wich is becomming a problem with shrinking manufacturing sizes as the packages have to get finer and finer as well wich costs more money.

cadaveca, what do you mean with if they need a crossbar to use the hyper transport bus? all the communication from the cpus is hooked up to the crossbar, and the corssbar is hooked up to the cpus. afaik the two cpus can even access each others cache through the crossbar, but im not sure about that.