amd dual core preview

[saaya]

cadeva, the fx is treated different, but its pretty much just an unlocked a64... its only marketing, theres nothing really different in this cpu compared to an a64 with 1mb L2 cache, other than the unlocked multis

EMC2, thx a lot didnt know the current cpus already have the x-switch inside, all 90nm cpus or already the 130nm cpus?
if they added it for the 90nm cpus that finally explains the slight performence boost over 130nm and why amd didnt comment about the boost

can you explain 3) in more detail again?

They (940 cus?) have fewer signals brought out from the memory controller. (compared to 939 socket CPUs)

dont really understand what you mean with fewer signals

5) In server versions, the master CPU uses one link to interface to the MB chipset and the other 2 links are used for interprocessor communication with other physical CPUs. For the "slave" CPUs, all links are used for interprocessor communications.

ahhhhh veryy interesting! now i get it, thx

6) The differences in the two memory controller configurations deal with the way clocks and control strobes are configured, with the 939 socket variants having an A/B set of pins to decrease loading on the signals.

hmmm is this what you are referring to in 3) ?

8) Currently CPU-IDs are set aside for 16 CPUs and the HT link routing table for 8 route entries/nodes (i.e. 8 dual-core CPUs).

alright! you can read my mind
you answered a question id ditn even write down yet

yes, this all cleared a lot of confusion, at least the confusion i got in over the X2's in MP and the HT links assignment

do you think amd will add a 4th HT link to cpus? or doesnt that make sence? i dont know what the bandwidth figures are atm and how much bandwidth the cpus actually use in an 8 way system, and how much they will probably use in an 8 way x2 (16 way) system. do you think a 4th ht link would make more sence, or adding yet another one or two slave cpus to each master cpu?

this is all very interesting, once you get how its set up you get how easy and well thougt the MP array of a64s is set up. this is really a nice step in the future, now all amd has to do is tweak things some more and move more and more of this MP array technology onto one die... the a64 architecture looks really very future proof.

intels move from single to multi and many cores is confusing me instead.
smithfiled is 2 cores on one die wich actually has a crossbar switch and is seen as one cpu by the chipset (according to intel, but i dont know if thats true or marketing), then they make a step backwards again by going 2 single dies with each one core only with pressler with the chipset handling it like SMP-on-a-package, and then will HAVE to make 2 steps forward again to more cores on one die, with a crossbar switch again sooner or later.

because packaging costs for the single cores they stuck on one package get smaller and smaller yet keep the same amount of pins or even need more... and the more cores they add the more communication pins they need to add overall, if they dont use a crossbar switch... and the chipset has to handle the different cores, and the mobo would need extra traces as well... atm it looks very confusing to me what intel does... and how they plan to smoothly transition their line from single to dual and then multi cores...