1) The crossbar switch exists in current single-core processors, all versions, as well as the coming dual-cores.

2) The 939-socket processor variants only bring one HT link to the outside world. There are extra signals brought out on the memory controller side of things (compared to the 940 socket CPUs).

3) The 940-socket processor variants have pins set aside for 3 HT links to the outside world. Only server versions have them wired up (2 and 3 link versions), "desktop" CPU version doesn't. They have fewer signals brought out from the memory controller. (compared to 939 socket CPUs)

4) In 939-socket and desktop 940 socket variants the single HT link is used to interface to the MB chipset.

5) In server versions, the master CPU uses one link to interface to the MB chipset and the other 2 links are used for interprocessor communication with other physical CPUs. For the "slave" CPUs, all links are used for interprocessor communications.

6) The differences in the two memory controller configurations deal with the way clocks and control strobes are configured, with the 939 socket variants having an A/B set of pins to decrease loading on the signals.

7) All HT links are bi-directional, non-duplexed (16 ins, 16 outs). The links can be configured for narrower configurations via internal CPU registers, 2,4,8,16.

8) Currently CPU-IDs are set aside for 16 CPUs and the HT link routing table for 8 route entries/nodes (i.e. 8 dual-core CPUs).

As AMD said, they have always been setup and ready for this

I think that covers all the queries and hopefully eliminates the confusion