Nf3 250/250gb/ultra Chipset Overclocking Issue !!!

[OSKAR_WU]

Currently there are two overclocking issue in NF3 250/250GB/Ultra Chipset ...

1 . External PHY SATA is useless once HTT clock > 240 MHz

Solution : No solution yet ...

2 . HTT clock PLL register is powered by stanby voltage , which means after you power down the system , the HTT clock register will remain the same before power down ... If you use low cpu ratio and high FSB combination , the board may fail to boot in next power up ... Ex : 3400+ cpu OC to 300 * 8 , in the next power up , CPU frequency will be 300 * 11 = 3300 mhz immediately

Solution :

1 . Always clear stanby power good signal to make HTT clock back to 200 mhz in every power up , but some stanby power good keeped funciton can not be used

2 . Always turn off stanby power after you powered down the system

3 . Use Mobile CPU instead of Desktop version

4 . Use Spread Spectrum Register to program HTT clock , which is not stanby powered keeped ... but it will cause other problem ...

[p4z1f1st]

Originally posted by OSKAR_WU
Currently there are two overclocking issue in NF3 250/250GB/Ultra Chipset ...

1 . External PHY SATA is useless once HTT clock > 240 MHz

Solution : No solution yet ...

u mean, external sATA-controllers for the pci-slot ?

[MightyOne]

No, I believe he means Onboard SATA Controllers such as the Silicon Image Sil3112 - as opposed to the integrated SATA Controller of the nF3-250. So these native ports haven't got a problem above 240MHz HTT? That'd be good news to me, since I don't plan to use more than 1-2 HDD ...

[OSKAR_WU]

Originally posted by MightyOne
No, I believe he means Onboard SATA Controllers such as the Silicon Image Sil3112 - as opposed to the integrated SATA Controller of the nF3-250. So these native ports haven't got a problem above 240MHz HTT? That'd be good news to me, since I don't plan to use more than 1-2 HDD ...

NF3 250/250GB/Ultra Chipset has two internal serial ATA controller , but only one of them has build in PHY interface ...
The other one controller needs an external PHY chip ...

Each controller has two serial ATA port ...

The two SATA port from this external PHY chip will be useless once HTT clock > 240MHz ...

But the other two port will be OK no matter what HTT clock is ...

[slavik]

1 . Always clear stanby power good signal to make HTT clock back to 200 mhz in every power up , but some stanby power good keeped funciton can not be used

what do you mean by that?

[p4z1f1st]

Originally posted by OSKAR_WU
NF3 250/250GB/Ultra Chipset has two internal serial ATA controller , but only one of them has build in PHY interface ...
The other one controller needs an external PHY chip ...

Each controller has two serial ATA port ...

The two SATA port from this external PHY chip will be useless once HTT clock > 240MHz ...

But the other two port will be OK no matter what HTT clock is ...

is there anything from which i can see, which of the both sATA-controller works with the external-PHY ?

so, that i can prevent testing first with one of the 2 connectors and then with the other ?

[mad mikee]

ANOTHER useful tidbit from the expert. :thumbsup:

SATA - That would explain the occasional thing I heard from time to time to only use the directly connected sata ports (1-2 near the AGP slot usually?)

HTT stuff would explain not-too-infrequent cold boot problems I have while awaiting the outcome of your(amoung other DFI peeps) handywork Is this addressed here on the 754 UT and how do we set up to do this please?

OR

Anyone have a pin-mod to lock the multi

[GreyBeard]

Oscar Wu is the BIOS engineer for DFI. So I am guessing these problems exist on the new DFI board and his post is to warn us in case our expections for this board get too out of hand (like that has not already happened).

Thanks for the info, Oscar. Great to see info like this coming from the source.

[Lifeless]

i have the same question as p4z1f1st, how do you know wich is wich?

[slavik]

Oskar is NOT the BIOS engineer ...

[cowpuppy]

Just so you guys know the Via chipsets are having the same problems. Aviod this all together and run a PCI raid card, this is one of the reasons that I can almost always pull a really nice clock out of my mombo's.

[EnJoY]

Originally posted by cowpuppy
Just so you guys know the Via chipsets are having the same problems. Aviod this all together and run a PCI raid card, this is one of the reasons that I can almost always pull a really nice clock out of my mombo's.

I'm sure thT R507 Mach 2 helps a bit too...

[eclypse]

So your saying that the PCI locks dont work for the sata raid on board chip?

[snowwie]

no, he's talking about the marvell adaptor (look at the dfi board http://www.dfi.com.tw/Upload/Product...0Gb_large2.gif)

the two sata connectors by the agp slot should be fine, they are using the built-in sata by the nvidia southbridge

same if you have a silicon image SATA chip, you should be fine too, because the SI chip is on the PCI bus

clear?

EDIT:

the marvell adaptor chip is not on the PCI bus, it is attached to the southbridge, via IDE? i think

[eclypse]

So the new DFI 250GB chipset board is using a marvell SATA chip insted of the silicon sata found on other 250 chipset boards eh?

If thats true, its good to know that i'll loose my raid setup when i switch from my current Epox board.. Time to back that raid up.

So basicly on the new DFI we want to use the SATA ports that are built in to the chipset?

Ok cool if thats all correct

[mad mikee]

the 3112/3114 is a whole separate SATA subsystem chip

the marvel chip is a driver like the network phy, 1394 phy, usb phy, etc that helps support the ON-CHIP nforce subsystems.

On the nf3, 2 ports run right off the nvidia chip (my guess is that is all nvidia alloc'ed power for) and the 2 ports further down are 'amplified' by the marvel driver chip and that chip does have a problem running 'out of spec'

Gee, this sounds like something familiar based on that which I just spouted heh? (LAN and USB issues?) who knows????

[OSKAR_WU]

Originally posted by slavik
1 . Always clear stanby power good signal to make HTT clock back to 200 mhz in every power up , but some stanby power good keeped funciton can not be used

what do you mean by that?

Some of the chipset circuits are powered by stanby voltage , some are powered by main power ...

Signal/register status powered by main power will be lost once the main power is turned off or reset#/powergood# singla is activated ...

But signal/register status powered by stanby voltage will still be keeped until stanby voltage is gone or stanby powergood# signal is activated ...

Stanby Power Good is a signal pin of the chipset , chipset will use it to determine if the stanby power is valid and determine the reset state of certain logic powered by stanby voltage ...

If the status of this pin changed , the chipset will reset all the signal/register status powered by stanby voltage to default ... It's like you just turn on the AC power of the power supply ...

" Always clear stanby power good signal to make HTT clock back to 200 mhz in every power up " will be something like you turn off the stanby voltage (when AC power is on , stanby voltage will be exist ) and turn it on again ...

[OSKAR_WU]

Originally posted by p4z1f1st
is there anything from which i can see, which of the both sATA-controller works with the external-PHY ?

so, that i can prevent testing first with one of the 2 connectors and then with the other ?

Currently there are two S-ATA 2 port PHY chip approved by nvidia , marvell 88SR3020 and Silicon Image SiI3012 ... If there are S-ATA ports very close to such kind of chip , that's it ...

[OSKAR_WU]

Originally posted by mad mikee
ANOTHER useful tidbit from the expert. :thumbsup:

SATA - That would explain the occasional thing I heard from time to time to only use the directly connected sata ports (1-2 near the AGP slot usually?)

HTT stuff would explain not-too-infrequent cold boot problems I have while awaiting the outcome of your(amoung other DFI peeps) handywork Is this addressed here on the 754 UT and how do we set up to do this please?

OR

Anyone have a pin-mod to lock the multi

Using spread spectrum register will be the best way to avoid this question but it will cause some other question ...

1 . If there is USB storage device exist during system booting into OS , te system will hang up ... Plug it until OS finished loading will be OK ...

2 . HTT clock can not be keeped after STR(suspend to ram) resume back ... If BIOS force to program the spectrum register will cause hang up ...

3 . You can not use NF3 clock gen utility from Frank , it may cause hang up ...

[p4z1f1st]

Originally posted by OSKAR_WU
Currently there are two S-ATA 2 port PHY chip approved by nvidia , marvell 88SR3020 and Silicon Image SiI3012 ... If there are S-ATA ports very close to such kind of chip , that's it ...

ok, good to know, that we shall use the 2sATA-ports farer from the PHY-chip

thanks

[OSKAR_WU]

Originally posted by eclypse
So the new DFI 250GB chipset board is using a marvell SATA chip insted of the silicon sata found on other 250 chipset boards eh?

If thats true, its good to know that i'll loose my raid setup when i switch from my current Epox board.. Time to back that raid up.

So basicly on the new DFI we want to use the SATA ports that are built in to the chipset?

Ok cool if thats all correct

Epox 8KDA3+ does not have external SATA PHY chip on board , but it does have the serial ATA port from internal SATA PHY ... If the previous RAID set is build by the two SATA port , it should work in any other NF3-250 board Internal/External PHY SATA port ... But if the RAID set is build by 3112A/3512 or 3114 PCI SATA controller , it can not be used by NV SATA port ...

[Ubermann]

What about regular IDE ?
Anything particular i should have in mind when overlocking and using ide and no sata?

[OSKAR_WU]

Originally posted by Ubermann
What about regular IDE ?
Anything particular i should have in mind when overlocking and using ide and no sata?

No OC related trouble found in IDE and internal SATA PHY port yet ... only External SATA PHY port have the problem ...

[chickenrun]

Hi,

I just got the board this monday and plugged my existing RAID array (on MSI K8N Neo SATA 3&4 - below the CPU) into the SATA 3&4 on the board - and it works

Here's a pic of the Marvell chip on the DFI... it's the little one above the SATA connectors and located in the right lower corner of the board



The bug concerns not only the related chipset (I think everybody realized that you will have to use SATA 3&4 to avoid trouble at higher FSB), but rather the number of DDR modules you're using...
I always had trouble (and not only me) with my MSI to go higher than FSB 230 with two modules (either 2x256 or 2x512, both OCZ) installed... it seems it hasn't been figured out whether really the raid causes the sys to hang under this config or it just relates to the mem-controller onboard the cpu which cannot handle both modules (and only specific types of ram) at higher FSBs...

[Bourch]

So now, we know how to bypass the SATA problem.
About the HTT & Multi one. Are correct those solutions?
- Use no bios OC but clockgen windows utility.
- Turn off the PSU power button or take off the cable.
- And lastly I'm not 100% sure about what happens if I reboot win or push the reset button.

Oskar, I know that you have explained it but as I'm spanish I don't understand 100% of what you write. Sorry for asking once again