AMD "Steamroller/Excavator" -info, speculations and experience

[FlanK3r]

ASRock Crosshair VI Extreme :-D....Or HD 8970 dx11 . I think, it is somethig from this hacking: http://www.hackingtricks.org/hacking...t-the-results/

[AlleyViper]

Such high stock vcore looks funny too.

[xVeinx]

http://www.crucial.com/promo/DDR4.aspx

[FlanK3r]

Excavator:

http://www.planet3dnow.de/cgi-bin/ne...?id=1368122313

[FlanK3r]

AMD today officially announced its China headquarters in Beijing Raycom Infotech Park and IEEE Bei ******* pter Excavator details of the specific architecture of the next generation. According to AMD's AMD AMD Excavator history of innovation largest architecture, the first of its the cluster modular architecture used since the inception of the bulldozer speculated that multi-threaded SPMT technology. In addition, the first comprehensive integration of the improved version of the next generation GCN Computer Unit, and reconfigurable technology arithmetic unit can be re-constitute in each CU 64 FMA can only support the Scalar Unit the four support 256bit AVX complex vector or eight 256bit Add / the MUL operation of the unit is directly connected to a module. At the same time, IEEE Bei ******* pter test results announced by AMD with the IEEE Society on a 28nm process Excavator processor Beta SPEC. Although only using the 28nm process, the frequency only 4G, but just a 4M8C4CU a simplified version, but its performance has been quite a lot
Speculated that the strong reconfigurable ability makes its application adaptability lead to high floating point performance reasons. Introduction of SpMT did not lead to the integer performance data have greatly improved, but we found very few relate to a large number of uncertain process integer on this processor performance even leading E3-1230 V2 9 times.



Speculated that multi-threading technology (Speculative Multithreading, SpMT) is developed speculatively execute multiple threads to thread-level parallelism, superscalar processor performance. By additional hardware units, such as thread synchronization unit (Thread Synchronization Unit, TSU), the thread context Sheet (Thread Context Table TCT) and thread memory history table (Thread Memory History, TMH), extends the transactional memory system to improve instruction set based on the wave scalar system the structure (the Wave Sealar ISA) to achieve WaveCache simulator's performance. It also proposed a new two thread-level transaction commit mechanism. Finally, six from the SPEC, Media and Mibench test procedures set true test procedures to assess speculated that the performance of multi-threaded WaveCache (SpMT WaveCache). The experiments show that the the SPMT WaveCache than 2 to 3 times the performance superscalar system structure is an effective method for the development of dynamic data flow computer performance


http://diybbs.zol.com.cn/11/11_106489.html

[Olivon]

Thanks FlanK3r

So Excavator is APU design only ?

[informal]

Thanks FlanK3r

So Excavator is APU design only ?

Yeah I think it is. For server parts it will feature more x86 "modules" but they might share the same GPU or we will just have one 4CU/8T/GCN "unit" as base unit and AMD will use it like lego for future server parts (gluing 3 or 4 of these on one die). Good news is that FINALLY the Fusion design is going to pay the due dividends.

[xVeinx]

In server then the GCN unit essentially becomes a "coprocessor" so to speak?

[The Stilt]

http://www.crucial.com/promo/DDR4.aspx

DDR4 is quite pointless, unless they reach frequencies higher than DDR-3000.
According to Micron their DDR4 parts will operate up to DDR-2400 at the launch.
No doubt they will be much more expensive than DDR3 at that point.

Kaveri will require atleast DDR-2666 DRAM (in 2x 64-bit or 1x 128-bit configuration) in order to fully saturate the GPU, even at stock frequencies (estimated). Even at that speed, the memory bandwidth (MB/s per PPI) would be 20-70% lower than on AMD NI / SI discrete cards.

I would assume there is plenty of overclocking potential too, so the bandwidth would soon become a major issue again.
Raise the GPU frequency by 20% from the stock and you'll need ~DDR-3200 for the same MB/s per PPI.

In other hand... A 4x 64-bit / 2x 128-bit configuration would provide the same bandwidth at half of the frequency

All of this is pure speculation of course

[FlanK3r]

yes, is long time for SR FX or Excavator...Maybe he thought DDR4 for Excavator. Btw, someone from AMD helped you or still not much good support ? Dont give up with TCIK ....

[xVeinx]

I meant for kaveri, actually. I'm no expert of such matters obviously , but I thought that the timing of the release might coincide with products that actually used it. Kaveri has me intrigued; I'm still reading and trying to understand the arch however .

[zir_blazer]

http://www.crucial.com/promo/DDR4.aspx

The DDR-4 chips sorting looks fun. It may look like it was impressive, but that's how current Quad Rank DDR-3 server modules looks like, here and here. I doubt you're going to see that in your regular Desktop machine.

[Hans de Vries]

AMD today officially announced its China headquarters in Beijing Raycom Infotech Park and IEEE

Officially launched at April 1st?

http://translate.google.com/translat...p%2F2244746760

Hans

[FlanK3r]

haha, OMG.... So...back to reality

[Olivon]

Nice find Hans

[FlanK3r]

not all news are fake news..

one interesting (and seems legit) is here:
http://www.xtremesystems.org/forums/...-Devil-May-Cry

[VulgarHandle]

If that is Kaveri, that would make it the first public demonstration of it running on socket FM2. Something most only speculated on, and others claimed without disclosing a source (like me).

[The Stilt]

I don't know if they could make quad channel to work on existing FM2 motherboards, however if they can't it is game over for FM2 anyway. Obviously you cannot have GDDR5 on existing FM2 motherboards.

If Kaveri has a 512SP GPU operating at 800MHz, the PPI would be 409.6 (512 * (800/1000)).

The 7660D in Trinity, which has PPI of 307.2 (384 * (800/1000)) can already over saturate the memory bandwidth provided by the 2x 64-bit DRAM interface at DDR-2133.

HD 7970 GHz Edition = 133.9MB/s per PPI (288000 / 2150.4)
7660D / DDR-2133 = 111.1MB/s per PPI (34128 / 307.2).
7660D / DDR-2400 = 125MB/s per PPI (38400 / 307.2)
Kaveri / DDR-2133 = 83.3MB/s per PPI (34128 / 409.6).
Kaveri / DDR-2400 = 93.7MB/s per PPI (38400 / 409.6).

Even at DDR-2400 the GPU on Kaveri would be seriously bottle necked.
There is no other way out than using either GDDR5 for the GPU or 4x 64-bit (quad channel) DRAM.

[VulgarHandle]

As to GDDR5, that ability is geared to tech specific, or, embedded solutions (as pointed out in the article referenced by Flank3r). PS4 for instance. We truly yet to fully understand all the benefits of CPU and GPU sharing both physical and virtual memory, including bandwidth behaviors. But the GPU will likely always be the bottleneck for APUs, even with GDDR5. AMD would really have to gain some clout if they could force the market to make such a leap in memory standard.

Remember, while a new socket is certain, an upgrade path is important too. For many current Trinity owners, it's good for them to know there will be options should their current APU die. If they can't afford APU+MOBO+RAM, they can just get an APU, and later get MOBO+RAM.

For enthusiasts.... Newegg just listed the AMD A4-4000 Richland APU for $49.99USD shipped, $5 cheaper than the A4-5300 Trinity.
http://www.newegg.com/Product/Produc...82E16819113343

[FlanK3r]

Motherboard FM2+ for Kaveri

http://wccftech.com/asus-shows-a88xm...kaveri-apus-2/

[Evantaur]

Motherboard FM2+ for Kaveri

http://wccftech.com/asus-shows-a88xm...kaveri-apus-2/

if you only could buy one :P

[demonkevy666]

Can someone post the Steamroller die shots, with the comparisons shots too?

[NoM$_YesLinux]

Motherboard FM2+ for Kaveri

http://wccftech.com/asus-shows-a88xm...kaveri-apus-2/

With exception of the new FM2+ socket, it looks identical the F2A85-M PRO.

[Evantaur]

According to the latest AMD server roadmap, there will not be a Steamroller based CPU with more than 4 cores and the high performance segment will only see a piledriver refresh code named Warsaw on 32nm with only benefit being lower power consumption.

http://linustechtips.com/main/topic/...cpus-from-amd/

sad if true

[haylui]

http://linustechtips.com/main/topic/...cpus-from-amd/

sad if true

if this is the prelude of shifting towards HUMA and compilers could really make use of APU, perhaps 4 SR cores could have the performance of FP in 8 or even 12 core Piledriver..?