Quote Originally Posted by nachtfalke View Post
This board loves BBSE too
Nice start, now let's see 32M action iso 1M

Quote Originally Posted by nickshih View Post
TCWL is the key ...if u cant tight it ... then cl5 will be slower ....

u can try to loose some subtiming .. TRRSR TWWSR etc.. some cant be 1 . only 2~3 is proper . it is depends on ur memory .
I tought tRRSR and tWWSR are lowest value 4 Nick ? Doesn't setting a lower value result in eg value 7 ? Nice work on the DIMM compatibility ASRock ! Top Job !