AMD "Piledriver" refresh of Zambezi - info, speculations, test, fans

[itsmydamnation]

Thats not a very good way of guessing performance increase, turbo is not an off or on switch. It ignores any delta in head room between bulldozer based SOC's and piledriver based SOC's. If you look at Trinity based SOC's and the fact they can get a 3.4/4.0 quadcore with a 384:24:8 ALU/mtu/rops @ 700mhz in a 65watt TDP when the GPU alone would pull somewhere around 35-40 watts ( the most efficient Turks pro pulls 45watts) it is obvious that there is significant headroom when operating within the 3ghz power range.

Bulldozer struggles to get off base clock in high throughput Floating point workloads and this can be seen with its very high turbo's. That's a big reason why your 5.4% clock increase isn't a very meaningful number. Trinity on the other hand has comparable clocks, lower base to turbo delta's, lower TDP and a GPU. To put it simply you can't make assumptions about how piledriver will clock based of bulldozers experience. One of the big reason for this is because the high power draw areas have been transitioned from soft flip flops to hard flip flops.

From there you also have to consider Integer and Floating point workloads separately. Integer workloads are up 10%-15% per clock vs bulldozer. Floating point on the other hand is less as part of the FPU wasn't broken like it was with bulldozer, it still benefits from bigger TLB's more flexibility in the LSU etc depending on workloads 0%-7% per clock has been seen for Trinity has been seen.

So i think your clock increase is to pessimistic and the "IPC" increase is way to variable to have a single value.

its now 1:30am and this dyslexic mans going to bed ( sorry if this post is unreadable, i tried but im tired......lol)


edit:

I thought the biggest change was the new resonant clock mesh design?

thats one of the big main things. going hard flip flops is another. These are physical changes, if your just taking about an architecture and not how it is implemented then that kind of stuff is abstracted away.

[informal]

Well my point is that no matter how you look at the average "IPC" and average clock uplifts,you will end up with what AMD Projected themselves: 10-15% performance jump versus FX8150. That's all. This is pretty decent and will put FX8350 very close (if not faster) to 3770K in various threaded workloads. Single-thread workloads will be still intel's domain,while they will surely be faster on Vishera(vs FX8150).

[tbone8ty]

Obr previewing Fx-8300 this weekend

http://www.obr-hardware.com/2012/08/...-this.html?m=1

[charged3800z24]

Saw this at Techreport today.

http://techreport.com/articles.x/23485

[possessed]

some more info on anandtech
http://www.anandtech.com/show/6201/a...r-architecture

[FlanK3r]

but this is more about Steamroller, not about Vishera ...Maybe next new thread?

[tbone8ty]

Hmm yah new thread flank3r!

[Oliverda]

Obr previewing Fx-8300 this weekend

http://www.obr-hardware.com/2012/08/...-this.html?m=1

Ohh God, please save us from that s**t.

I think he has nothing. We'll see some fake results again. I could do the same easily.

[AsterixXx]

Fake results? Unfortunately he was right about Bulldozer before the launch when almost nobody believed him. Ok, maybe now he has nothing but a year ago he was right .

[Alex-Ro]

Red Octomber is coming,who knows,thing is samples of new bulldozer should appear pretty soon

[cezar]

Vishera to be previewed in 2 weeks:

http://news.softpedia.com/news/AMD-s...s-288948.shtml

[The Stilt]

That is not a Vishera.
It is just the Bulldozer C0 spin.

Strikethrough tags are not working on Xtreme, but I guess you´ll get the point.

[Mechanical Man]

Strikethrough tags are not working on Xtreme, but I guess you´ll get the point.

So how many wheels is on ur avatar piledriver?

[demonkevy666]

Ohh God, please save us from that s**t.

I think he has nothing. We'll see some fake results again. I could do the same easily.

I tend to not want to believe a man who thinks a 5770 is faster then a 5870.

Fake results? Unfortunately he was right about Bulldozer before the launch when almost nobody believed him. Ok, maybe now he has nothing but a year ago he was right .

No he was only right because, he got a hold of a chip.

The real question is how is he getting a hold of these chips ?

[tbone8ty]

http://4.bp.blogspot.com/-n_mDl-4Vlg...mparaison2.jpg

Piledriver die shot

[haylui]

http://4.bp.blogspot.com/-n_mDl-4Vlg...mparaison2.jpg

Piledriver die shot

looks a lot of differences compared with bd.

[nunchucka]

color wise yes...

[repman]

By the looks of it, he just inverted colours

[itsmydamnation]

By the looks of it, he just inverted colours

to me it looks like its missing the additional sram bank in the front end

http://forum.beyond3d.com/showthread.php?p=1610388

if he was going to fake it, he could at least paste in the already available piledriver module die shots.

[repman]

to me it looks like its missing the additional sram bank in the front end

http://forum.beyond3d.com/showthread.php?p=1610388

if he was going to fake it, he could at least paste in the already available piledriver module die shots.

But the image that *** posted, the PD image is exactly the same as the BD, even the SRAM bank count is the same I can't notice anything different.
Could it be that the changes of PD aren't evident from the die shots? (although I doubt it)

[Evantaur]

if he was going to fake it, he could at least paste in the already available piledriver module die shots.

but hue slider is more fun!

[Barr3l Rid3r]

What a shamee.,..

[Oliverda]

Fake results? Unfortunately he was right about Bulldozer before the launch when almost nobody believed him. Ok, maybe now he has nothing but a year ago he was right .

Who talked about Bulldozer?

That man is a walking bulls**t river regardless of the topic.

[Monkeywoman]

At up to 5 dual-core pairs per die, only two channels of DDR3 memory might not feed the CPU as well as four channels of DDR3-1866 (possibly even 2133, looking at Inphi's register clock chip announcement this summer for such ECC buffered DIMM support) on the Ivy Bridge EP next year. The effects on memory bound apps including the increasingly popular 'big data' and analytics, would be serious.

Combining AMD eDRAM and backside L4 cache die approach could give AMD a, say, 128 MB or even 256 MB dedicated L4 cache sitting on a wide, even 1024 bit, bus within the chip packaging, and massively help counter the bandwidth drawback of the two DDR channels per die. In some apps where the code and/or big loops of data fit within that footprint, you could get over double the real life performance just this way.

2014 is far but if AMD is staying in the same socket then they will have to get creative to achieve substantial performance gain.

source: http://vr-zone.com/articles/how-amd-...013/17105.html

[Yeroon]

I thought piledriver was the last of the am3+ chips, only to fix the shortcomings of the bulldozers and that the newest socket isn't known ATM.
Maybe apu/cpu sockets merge? <<< Pure speculation on that, and a long shot too.