Introduction
Feeling somewhat curious about the reports that inferior TIM ships from the factory inside IB chips, I found myself taking my new 3770K out of the safety of its socket this afternoon and on to my desk where it went under the knife. About 15 min later, I finalized the divorce of its IHS and its PCB. It was surprisingly simple to do; a standard razor blade (0.009") and a little bit of patience was all that was required. After cleanup and application of fresh TIM, I sought to put a nice story together for you readers covering how to do procedure yourself and sharing my results and the methods used to arrive at them.
Removing the IHS from an i7-3770K
Maintain a level blade and gently insert it between the green part of the chip (PCB), and the silver part (IHS). I found it best to start on a corner. From what I've read, care needs to be taken not to scrap the PCB, as key parts of the chip reside very close to the surface. Slowly and gently, rock the blade between the two until it penetrates. Then slide it around the perimeter. See the pics to visualize the die so you don't push the blade in too far. The IHS will come off easily once you have completed severing the glue which is removed with gentle scraping with credit card or finger nails; isopropyl alcohol doesn't help much. When finished cleaning up both pieces, apply TIM to the die, place it back in the MB, and gently place the IHS on it. Lock it into place in the MB with the mounting bracket that will hold the IHS to the chip securely thus keeping you from having to glue down the IHS.
I'm a pretty big fan of Arctic Silver 5 (AS5) and used it both on the die, and on the outside of the IHS. My "factory" configuration had a good 120 h of load/idle cycles on it. As you probably know, AS5 has a breakin period associated with it...200 h according to Arctic Silver Incorporated. You will see this reflected in the data.
Data Collection and Analysis
I wanted to generate robust and statically valid conclusions about the efficiency of entire process; results are drawn from a fairly large data set looking at the populations of temperatures and VID values.
Temps and vcore values were collected via lm-sensors driven by a simple shell script which queried it every 2 sec logging the results to a file.
Example:
These data were annotated and distributions were analyzed with some basic statics to see if the different TIMs under the IHS really makes a difference. Note that there are too many variable to control for this sort of analysis to be iron clad. For example, TIM spreading variations, mounting techniques, variations in hardware, etc. Even room temp can't be rigorously controlled. My office is air conditioned and ranged from 75-77 F when I ran the stress tests.Code:dts,vcc,temp,core0,core1,core2,core3,120mm_rpm,120mm_pwm,140mm_rpm,140mm_pwm 07-28-12 09:19:31 AM,1.280,66.0,58.0,63.0,65.0,60.0,1285,255,1225,255 07-28-12 09:19:34 AM,1.272,65.0,57.0,62.0,65.0,61.0,1300,255,1216,255 07-28-12 09:19:36 AM,1.272,64.0,59.0,63.0,66.0,59.0,1294,255,1226,255 ...
Methods of Stressing
I use linux, but fortunately, key stress testers are cross platform. Intel BurnTest for windows is based on linpack from Intel which is available for many platforms. The settings I used were 25k problem sizes and 25k leading dimensions with 4 KB alignment.
On top of linpack, I ran a compile job looped in the background (nice=19) set to use 8 threads to further scarfs-up any unused CPU cycles.
System Specs and Settings
Asus P8Z77-V Pro
Intel 3770K @ 45x100
Cooling is an NH-D14 with both fans; my system manages their speed but they are both running on max for the stress tests (1,200 RPM for the 140mm and 1,300 RPM for the 120mm).
The BIOS is running using a vcore in offset mode so the vcore is automatically controlled by the BIOS and is dependent on load. Mine is stable with a setting of +0.0200 and here are the other key voltages and settings in case you're wondering:
ResultsCode:VCCSA Voltage = 0.92500 CPU PLL Voltage = 1.5500 PCH Voltage = 1.06000 CPU Load-Line Calibration = Ultra High CPU Current Capability = 140 % CPU Power Response = Medium
I ran the stress test described above for ~2 h period and used the geometric mean of the temps per core as the "average" temperature over that time period. I repeated this for a total of 4 nights, but lost the data on day 1 due to an overwrite on my part! Here are the average corresponding temps per day; there is a nice decrease out to day 3 where it more or less plateaus off. Perhaps that is the AS5 "breaking-in." Also note the error bars correspond to the measured ambient temp which ranged between 75-77 F or 1.1 C. You can see that some values at day 3 and 4 are not different when accounting for this:
As well, here is a plot of the delta temp, that is, the values subtracted from the stock results indicating the magnitude of temperature decrease:
And to be sure this horse has been beaten well after it died, here are the results compiled in a table:
Conclusion
For this example, a decrease in load temps was observed after delidding an Intel 3770K and replacing the factory TIM with AS5. The magnitude of the temperature reduction was not even across all cores, and ranged for -2C to -12C. The data are consistent with Arctic Silver Inc.'s claim that the TIM requires a break in period. This has to be one of the cheapest modifications to gain lower operating temperatures which can be converted into higher voltage and likely higher clock rates. The unevenness of the decrease is puzzling. Since the overall rank order of temps was retained after the TIM replacement, perhaps it has to do with some physical unevenness in the IHS, in the base of the HS, or on the CPU die itself. Investigating this is beyond the scope of this exercise.
Supporting Data
Link to my shell used to log the data.
Link to my shell script used to run gcc in the background.
Link to the entire data file (tab separated) should you wish to dig into it.
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Originally Posted by churchy
q9550 @ 444 x 8.5 1.3v - Venomous X 
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