Intel's MIC, now officially christened Xeon Phi, was known to have been seeded for a while across few dozen test sites worldwide, including our region - mostly in supercomputers and workstations as a computational accelerator. While the performance of the seed units was either not that great or plain & simple confidential, its X86 + SIMD base was supposed to greatly help programmers comfortably make use of it without the CUDA or OpenCL complications.
And, it did work - according to our high level sources in both China and Singapore, in some cases the code porting time differential is huge, like a few months to handle CUDA becoming few days to complete the MIC code port.
So, right after the ISC supercomputer show in Germany, there were two interesting updates from our friends.
First, Intel Xeon Phi has managed to kick out the GPUs as the FP (floating point) accelerator in several very large upcoming deals worldwide, including some in the 100 PFLOPs range, for 2013 and 2014. We are talking here about the replacements for the current single-digit leaders of the TOP 500 list, that right now use Nvidia Tesla as the accelerator. A, say, 100 PFLOPs supercomputer composed of an equal proportion of, say, Ivy Bridge EP Xeons and Xeon Phi's - i.e. each dual CPU node having dual Phi - would have in excess of 80,000 Xeon CPUs and 80,000 MICs for the users to play with, as a single machine. Most importantly, like it or not, as a single homogeneous X86 instruction set machine.
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