Xeon Phi

[villa1n]

*did some searches couldnt find any threads*

http://www.anandtech.com/show/6017/i...ic-goes-retail

As conference season is in full swing, this week’s big technical conference is the 2012 International Supercomputing Conference (ISC) taking place over in Hamburg, Germany. ISC is one of the traditional venues for major supercomputing and high performance computing (HPC) announcements and this year is no exception. Several companies will be showing off their wares, but perhaps the biggest announcement of the week is from Intel. After having worked on the project for over half a decade in some form or another they’re finally ready to take a stab at the parallel computing market by bringing their first Many Integrated Core (MIC) product to market. Knights Corner, the codename for the first such product, will be the launch product for a brand new family of Intel co-processors, which the company is introducing as the Xeon Phi family.

So what do we think, will this disrupt the HPC market with the ease of use programmability and the fact it has it has its own mini os onboard? The teraflop number is a bit suspect, I d imagine this number is combined with the main cpu it is co-processing for and thus putting its actual throughput at around 700 Gflops or on par with todays GPU offerings.

Thoughts?

[kl0012]

The teraflop number is a bit suspect, I d imagine this number is combined with the main cpu it is co-processing for and thus putting its actual throughput at around 700 Gflops or on par with todays GPU offerings.

Thoughts?

Intel insist 1 TFLOP/s sustained performance in DGEMM.
http://software.intel.com/en-us/blog...bit-emotional/

[villa1n]

Intel insist 1 TFLOP/s sustained performance in DGEMM.
http://software.intel.com/en-us/blog...bit-emotional/

from Anand

The Top 500 results score achieves 118 TFlop with 9800 cores. Making the big assumption that all of the performance was from a 50 core MIC card, that'd put performance per card at 602 Gflop double precision. At 64 cores per card, double precision performance would be 770 Gflop. Chances are that part of the result also used the SandyBridge CPU's, otherwise it would have made more sense to go with the quad core Xeons to make the power consumption figures look better. How much this would skew results would depend on the system configuration. Two Xeon E5-2670's per MIC card would have a bigger increase the performance per card rating than one Xeon E5-2670 for four MIC cards would.

There are a few factors that could raise those scores. As a prototype, clock speeds were likely conservative and there is also the possibility of turbo coming into play. Further more results for a single card and host will likely be higher due to the removal of network overhead.

Regardless, these results paint Xeon Phi as merely competitive instead of having a decisive performance edge over its GPU counter parts.

The DGEMM at 20W's is pretty crazy though, very data center friendly.

[ice_chill]

What can you do with a TERAFlop ?

And what does double precision do that single precision isn't good enough for ?

[Darakian]

What can you do with a TERAFlop ?

Compute one trillion floating point operations a second

And what does double precision do that single precision isn't good enough for ?

About 32 bits.

Sky's the limit man. With that kind of compute power you could model the thermals of your room with NOAA level detail if you really wanted to.

Edit:
Put another way
MOAR BECAUSE MOAR!

[DeltZ]

Single precision IEEE:
"This gives from 6 to 9 significant decimal digits precision" (from wiki)

There are plenty of calculations which need higher precision than this. Even an audio DAC can probably make use of double.

[Otis11]

A thread over at the WCG section for those of you who are interested...

[kl0012]

http://vr-zone.com/articles/intel-xe...ome/16410.html

Intel's MIC, now officially christened Xeon Phi, was known to have been seeded for a while across few dozen test sites worldwide, including our region - mostly in supercomputers and workstations as a computational accelerator. While the performance of the seed units was either not that great or plain & simple confidential, its X86 + SIMD base was supposed to greatly help programmers comfortably make use of it without the CUDA or OpenCL complications.
And, it did work - according to our high level sources in both China and Singapore, in some cases the code porting time differential is huge, like a few months to handle CUDA becoming few days to complete the MIC code port.

So, right after the ISC supercomputer show in Germany, there were two interesting updates from our friends.

First, Intel Xeon Phi has managed to kick out the GPUs as the FP (floating point) accelerator in several very large upcoming deals worldwide, including some in the 100 PFLOPs range, for 2013 and 2014. We are talking here about the replacements for the current single-digit leaders of the TOP 500 list, that right now use Nvidia Tesla as the accelerator. A, say, 100 PFLOPs supercomputer composed of an equal proportion of, say, Ivy Bridge EP Xeons and Xeon Phi's - i.e. each dual CPU node having dual Phi - would have in excess of 80,000 Xeon CPUs and 80,000 MICs for the users to play with, as a single machine. Most importantly, like it or not, as a single homogeneous X86 instruction set machine.