SuperPi32m 5Ghz Ivy All Out Challenge!

[Raja@ASUS]

got up to 1276mhz but it only cut 0.14s from 1250mhz run. That includes using Spi Booster on 0086.


cheapseats - 6:19:640 - 48x106.4 - 1276.5MHz - 9-12-8-30-86-1 - ASUS MVG - Exceleram EB3103A 4x2GB/PSC - 1.85V - air

4x2GB




Memtweaker Timing#2

CHB DIMM 0 is tricky .. will only run with different RTL & IOL for ranks 0 & 1.
Sometimes boots with both ranks at 41 & 4 but fails at Loop 6. Only passes 32M if Rank 0 is 40 & 3




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correct, CL values where WCL > CL is wasting time with PSC/BBSE.

this table was for Sandy + PSC, but the CL + WCL combinations for RTL & vDIMM scaling also apply to Ivy with PSC

the Hyper table was just a reference to show the differences in RTL scaling with PSC CL.



full thread and 32M tests:
CL|WCL|RTL performance (SB) : 32M scaling charts : PSC WCL > CL performance bug

Looks like Intel shifted the POST calculation to include WCL from SNB onwards. Previously these two were tied on X58 and P55. IO-L is buffer latency and allows RTL to be shifted to account for any IO delays from the DRAM buffers (there is also a clock skew offset but that value is internal and calculated during POST).


EDIT: I should add that IO-L is an offset, the base value it is added to shifts so adjustment does not always help. The shifting in the base value is due to read/write levelling drift. This manifests at speeds higher than DDR3-2000 depending upon the DIMMs used (some DIMMs are okay to DDR3-2400). Basically you have to get lucky with training for stability.


The effective RTL time is likely close to: 8 X ((1000/Uncore Freq)+ Clock skew)+tCL. The IOL likely moves a pointer at the IMC FIFO buffer for data arrival on top of the RTL time. Uncore freq should be around DRAM Freq on this platform. I had a quick look at SNB last year and it seemed that is what Intel had done, I would assume it is the same here.

-Raja