Rampage IV Extreme UEFI Guide for Overclocking

[Raja@ASUS]

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DRAM Ref Cycle Time: Also known as tRFC. Specifies the number of DRAM clocks that must elapse before a command can be issued to the DIMMs after a DRAM cell refresh.

DRAM Write Recovery Time: Defines the number of clock cycles that must elapse between a memory write operation and a precharge command. Most DRAM configurations will operate with a setting of 9 clocks up to DDR3-2500. Change to 12~16 clocks if experiencing instability.



DRAM Read to Precharge Time: Also known as tRTP. Specifies the spacing between the issuing of a read command and tRP (precharge) when a read is followed by a page close request. The minimum possible spacing is limited by DDR3 burst length which is 4 DRAM clocks. Most 2GB memory modules will operate fine with a setting of 4~6 clocks up to speeds of DDR3-2000 (depending upon the number of DIMMs used in tandem). High performance 4GB DIMMs (DDR3-2000+) can handle a setting of 4 clocks provided you are running 8GB of memory in total and that the processor memory controller is capable. If running more than 8GB expect to relax tRTP as memory frequency is increased.




DRAM Four Activate Window: Also known as tFAW. This timing specifies the number of DRAM clocks that must elapse before more than four Activate commands can be sent to the same rank. The minimum spacing is tRRD*4, and since we know that the minimum value of tRRD is 4 clocks, we know that the minimum value for tFAW at the chipset level is 16 DRAM clocks.


As the effects of tFAW spacing are only realised after four Activates to the same DIMM, the overall performance impact of tFAW is not large, however, benchmarks like Super Pi 32m can benefit by setting tFAW to the minimum possible value.


As with tRRD, setting tFAW below its lowest possible value will result in the memory controller reverting to the lowest possible value (16 DRAM clocks or tRRD * 4).




DRAM Write to Read Delay: Also known as tWTR. Sets the number of DRAM clocks to wait before issuing a read command after a write command. The minimum spacing is 4 clocks. As with tRTP this value may need to be increased according to memory density and memory frequency.

DRAM Write Latency: For the most part this setting can be left to Auto, and generally will default to Read CAS -1. So if CAS is set to 8 for example, Write CAS may default to 7. To facilitate stability at higher DDR3 speeds (over DDR3-2133) and if using 64GB of memory, then increasing Write CAS by 1~2 clocks should help at the expense of memory write speed performance. Older DIMMs may not POST if Write CAS is set over 8 clocks, so you will need to limit write IO by relaxing some of the Write to Write timings such as tWWDD and tWWDR and/or increasing VDIMM.

Third Timings




Most of these timings can be left on AUTO unless tweaking for SuperPi 32M.

tRRDR: Sets the read to read delay where the subsequent read requires the access of a different rank on the same DIMM. 3 clocks will work with most configurations at high memory frequencies. Only needs adjustment when double-sided DIMMs are used.

tRRDD: Sets the read to read delay where the subsequent read requires the access of a different DIMM. 3 clocks will work with most configurations.

tWWDR: Sets the write to write delay where the subsequent write command requires the access of a different rank on the same DIMM.

tWWDD: Sets the write to write delay where the subsequent write requires the access of a different DIMM. 3 clocks will work with most configurations.


tRWDR: Sets the delay period between a read command that is followed by a write command; where the write command requires the access of data from a different rank. A setting of 3 clocks suits most DIMM configurations all the way to DDR3-2133. Relax to 5~7 clocks only if you are experiencing stability issues when running in excess of 8GB of memory over DDR3-2300.

tRWDD: Sets the delay period between a read command that is followed by a write command; where the write command requires the access of data from a different rank or DIMM. A setting of 3 clocks suits most DIMM configurations all the way to DDR3-2133. Relax to 5~7 clocks only if you are experiencing stability issues when running in excess of 8GB of memory over DDR3-2300.


tWRDR: Sets the delay period between a write command that is followed by a read command; where the read command requires the access of data from a different rank. A value of 1 is possible on high performance memory. For higher density modules this value may need relaxing to 5~7 clocks as memory frequency is increased.



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tWRDD: Sets the delay period between a write command that is followed by a read command; where the read command requires the access of data from a different DIMM. A value of 1 is possible on high performance memory. For higher density modules this value may need relaxing to 5~6 clocks as memory frequency is increased.


tRWSR: Sets the read to write delay timing where the write follows a read on the same rank. Can be left to 3 clocks for most configurations. 1~2 clocks may be possible at lower memory frequencies depending upon module density (sub DDR3-1866). If experiencing instability after adjusting all other timings, then try a setting of 5~7 clocks.



tCCD: Sets the read to read delay where the subsequent read accesses a different column after a four clock burst. The minimum internal spacing is 4 DRAM clocks, if a setting of 0 is used the chipset will default to 4 clocks, a setting of 1 will set a spacing of 5 clocks and so on. For all overclocking, it is recommended that this setting is left at 4 clocks to maintain read performance.

DRAM RTL (all ranks and channels): Also known Round Trip Latency. RTL denotes the number of clock cycles it takes for a data to arrive at the memory controller after a read CAS command is issued. This value is specified in memory controller clock cycles (not DRAM clock cycles). On the Sandybridge architecture these values can safely be left on AUTO most of the time and do not need manual adjustment.

Should you wish to experiment, note that DRAM IOL should be changed, too. If delaying RTL, then delay IOL by 1~2 clocks for example.





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DRAM CLK Period: Can really affect performance and yet overclocking at the same time. A centered value of around 5 or 7 usually gives best performance but it may not be that great for overclocking. A value of 3 or 7 can be good for Command Rate 1T overclocking.


Enhanced Training (CHA-CHD): There is no definite best setting for Enhanced Training, usually though disabling it helps with overclocking on R4E

MCH Duty Sense (CHA-CHD): Again no definite best setting for MCH Duty Sense though using a lower value on CHA and CHC than the one used on CHB and CHD may be helpful. 15-19 perhaps are good values to experiment with.

Receiver Slew: Leave on Auto for most overclocking. Try a setting of Normal if experiencing instability when running memory over DDR3-2133.

Transmitter Slew: Leave on Auto for most overclocking. Try a setting of Normal if experiencing instability when running memory over DDR3-2133.

MCH Recheck: Forces memory to be rechecked to ensure only DIMMs that pass POST memory check are mapped to the OS. Leave on Auto unless experiencing instability. Try a setting of Disable if some DIMMs won't map to the OS.

RC Warm Boot Fast: Disables memory training when Enabled. If running at speeds over DDR3-2133, then Enable this setting once the memory is stable. Drift in memory training parameters may result in instability if this setting is left enabled and the system is booted multiple times or during sub-zero cooled benchmarking sessions. For all other purposes leave on Auto or Disabled.