Quote Originally Posted by OC Nub View Post
Have you tried using less PLL volage?
Not yet. My big issue was the cold boot thing. I think the Clock Gen Filter of 20UF fixes the issue, but when I was trouble shooting it at the time, I made a shotgun set of adjustments that worked really well. Because the cold boot issue was random, I am winding down each of the changes I made one at a time, so it is taking a while to test each change. So far I've been able to drop the VTT and VCCSA from 1.3v each, and now I have the Vcore offset working. I will try a PLL drop tomorrow after I let this current configuration cycle a few more times.