Quote Originally Posted by Smartidiot89 View Post
I find it hard to believe with a stepping, even with a new revision I'd raise an eyebrow. I will take 10-15% increase with Trinity as that is what I've heard from AMD and that this guy from Chiphell shows in hes results. 20% i don't think will happen with Piledriver, not IPC-wise - but IPC+clocks i find it very possible, even very likely.

AMD have already gone public that they aren't happy with GlobalFoundries performance with 32nm, and the power consumption of Bulldozer (especially overclocked) points the finger towards high leakage. I think there's alot that can/will/has be done, both on the design and manufacturing side.
The biggest issue is GF's crappy 32nm manufacturing tech.

Dresdenboy:

Some more power hungry units _seem_ to run at half the clock. Integer MUL shows a 2 cycle granularity in latency and a throughput of one every 2 (32 bit) or 4 (64 bit) cycles.

L2 cache latency is 18 (1 MB) or 20 (2 MB) cycles. It could be the case that it runs at half the clock too. Years ago an AMD designer (Jerry Moench) talked about half clocked L2 cache for "K9" in Stanford. Bobcat has a half clocked L2.

This is not about speed paths but about power consumption. Those 2 billion transistors cause a heck of a leakage.
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