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[informal]

Do you guys even read what I wrote? In floating point heavy code that employes all 8 threads Turbo will almost never engage. Turbo will engage accross all 8 integer cores though,but cinebench will use flexfp coprocessors most of the time where tdp will be maxed out. You can read all about bd exec. units power draw and clock characteristics at amd blogs past isscc event.

[Opteron146]

Do you guys even read what I wrote? In floating point heavy code that employes all 8 threads Turbo will almost never engage. Turbo will engage accross all 8 integer cores though,but cinebench will use flexfp coprocessors most of the time where tdp will be maxed out. You can read all about bd exec. units power draw and clock characteristics at amd blogs past isscc event.

I red but do you have a BD? So why should I believe you?
Cinebench11.5 scores are rather bad even CB10 is doing better. Hence I do not believe that the FPU is maxed out at all, especially as there is neither FMAC nor XOP/"MMX" code (the other 2 pipes in the FPU) used. Thus I think there is enough headroom for the 3,9Ghz Turbo stage. Anyways, we'll know in less than 1 week ;-)

If that does end up being the case, I will certainly get the 8100 instead!

Then you have to wait a few weeks longer, because there is only a 8120 and 8150 model at launch ;-)
However, there are 2 versions of the 8120, 125W and 95W, but from experience with the Phenom2s, I would assume that the 95W part will go directly into the OEM market to Dell, hp, etc.

[tifosi]

...but from experience with the Phenom2s, I would assume that the 95W part will go directly into the OEM market to Dell, hp, etc.

It took me less than 2 mins to find these in retail... and at one retailer!
http://www.newegg.com/Product/Produc...82E16819103856
http://www.newegg.com/Product/Produc...82E16819103809
http://www.newegg.com/Product/Produc...82E16819103921

[Opteron146]

It took me less than 2 mins to find these in retail... and at one retailer!
http://www.newegg.com/Product/Produc...82E16819103856
http://www.newegg.com/Product/Produc...82E16819103809
http://www.newegg.com/Product/Produc...82E16819103921

Well I should have been more specific. Yes, these are all 95W parts, but there is no 125W version of the same model. I was referring to the 1055T. Likewise to the FX8120 there are 2 versions of it, a 95W and a 125W:
http://products.amd.com/en-us/Deskto...?id=641&id=652

However, the 95W part just appeared recently in the etail market (2-3weeks back here in Europe), probably because OEMs are filling their stocks with Bulldozers now.
Also note that there is no "shop now" link for the 95W part in the above link.

[tifosi]

Well I should have been more specific. Yes, these are all 95W parts, but there is no 125W version of the same model. I was referring to the 1055T. Likewise to the FX8120 there are 2 versions of it, a 95W and a 125W:
http://products.amd.com/en-us/Deskto...?id=641&id=652

However, the 95W part just appeared recently in the etail market (2-3weeks back here in Europe), probably because OEMs are filling their stocks with Bulldozers now.
Also note that there is no "shop now" link for the 95W part in the above link.

Well yes, the parts are indeed different. However, your point was it would be shipped to OEM's and retail wouldn't see any (if at all). Unless it is a OEM special, like the 960T, where AMD clarified as much, i don't have a reason to believe that the 95W chip won't be seen in retail. If you look at it, Phenom II 945 is merely locked version of 940 at lower TDP. This being FX, i don't think AMD would muck about.

[Opteron146]

Well yes, the parts are indeed different. However, your point was it would be shipped to OEM's and retail wouldn't see any (if at all). Unless it is a OEM special, like the 960T, where AMD clarified as much, i don't have a reason to believe that the 95W chip won't be seen in retail. If you look at it, Phenom II 945 is merely locked version of 940 at lower TDP. This being FX, i don't think AMD would muck about.

Well the 945 was later in the C3 revision a plain, normal 95W part. The first 940/945 models with 125W were still C2. Nothing exciting about that, that's the normal process/stepping optimizing benefit. If you want to compare it to FX, then my point would be that the 8120 95W model will be scarce as hen's teeth in etail, because it will be an OEM only model and etail=we have to live with the 125W part or the 8100 95W model, instead. Then next year, when they'll launch 8170, there's maybe enough 95W 8120 for everybody. We'll see...

[tifosi]

...there's maybe enough 95W 8120 for everybody. We'll see...

Well, process is only going to improve with time. This will allow some headroom and a chip with a lower TDP is not so far fetched an idea, as you seem to propose. There were also server MC chips, some of which now are there with lower TDP.

[imamage]

I red but do you have a BD? So why should I believe you?
Cinebench11.5 scores are rather bad even CB10 is doing better. Hence I do not believe that the FPU is maxed out at all, especially as there is neither FMAC nor XOP/"MMX" code (the other 2 pipes in the FPU) used. Thus I think there is enough headroom for the 3,9Ghz Turbo stage. Anyways, we'll know in less than 1 week ;-)

Dang, I wish I have one before Retail Launch !!!

[dess]

Do you guys even read what I wrote? In floating point heavy code that employes all 8 threads Turbo will almost never engage. Turbo will engage accross all 8 integer cores though,but cinebench will use flexfp coprocessors most of the time where tdp will be maxed out. You can read all about bd exec. units power draw and clock characteristics at amd blogs past isscc event.

You have a point, but I think Cinebench uses mostly scalar maths, utilizing only the 1/4 or 1/2 of the 128 bit wide engines (depending on that if it uses single or double precision).

Also, it doesn't use FMA, so the underlaying FADD and FMUL units in an FMAC never work at once (or at least only one execution starts, per cycle).

0.5 x 0.5 = 0.25 -> 1/4 FPU utilization/thread (with MT)
0.25 x 0.5 = 0.125 -> 1/8 FPU utilization/thread (with MT)

Of course, it's quite theoretical as the sharing of the FPU is not exactly 50% per thread per module all the time, and these are the peak values.

It looks like it almost has enough FP resources to get the same performance as two "full" cores, the exception being if two 256-bit instructions were issued at once - though the capability to do that requires much more (largely unused) die area.
So I would think two thread scaling (in one module) is largely a matter of the shared front-end's capability to feed the execution resources (as well as memory bandwidth, latencies etc which needs to be improved the more cores you have)

Depends on if FMA is utilized or not and that if only one or two threads run in a given module, I think. AFAIK the FADD and FMUL units in the K10 cores are capable of working (or starting/finishing) parallelly. With BD, with regular code you can't have the underlaying FADD and FMUL units utilized (or new execution started/finished) at once, in a given FMAC, unless you use FMA code. And you have only one FMAC per thread in case both threads needs them at once...

So, with a single-threaded (or one thread per module) regular code it will perform comparable to K10 (because the second FMAC can be utilized anytime), but if more than 4 threads are running scaling will be worse.

But, perhaps I'm wrong somewhere. Feel free to correct me, then.