AMD Zambezi news, info, fans !

[Manicdan]

Shouldn't an hypothetical Phenom II X8 @ 4.8Ghz score between 10 a 10.5 points in CB11.5?

the old architecture gets about .3 pts per ghz per core, round down a little for inefficiencies

so up to 8.4pts at 3.6ghz for an octo PII
11.3 pts for 4.8ghz

keep in mind that in the CB11.5 thread weve seen a half point spread even at the same ghz. but we also see people getting mid 7pts in mid 4ghz. so these results look bad

[BeepBeep2]

Shouldn't an hypothetical Phenom II X8 @ 4.8Ghz score between 10 a 10.5 points in CB11.5?

the old architecture gets about .3 pts per ghz per core, round down a little for inefficiencies

so up to 8.4pts at 3.6ghz for an octo PII
11.3 pts for 4.8ghz

keep in mind that in the CB11.5 thread weve seen a half point spread even at the same ghz. but we also see people getting mid 7pts in mid 4ghz. so these results look bad

You guys seem to have missed what chew said...
1. Bulldozer functions like a 4 core that is able to execute 8 threads. You get roughly 5x scaling in CB from one to eight cores. (Better than HT) I don't care what PR tells you, that's how it works. (Unless new charts have come out with magical 7.x scaling?)
2. You have two options with the "STARS" core.
...Option 1. Shrink X6 (probably with redesigned Llano "STARS" core, so 3% IPC increase lets say) and increase frequency a tad. Lets say that this arch. will do 4.5 Ghz.
...Option 2. Add more cores, most likely decrease IPC from Thuban or keep it the same using Llano's tweaked core...lets say this arch will do 4.1 Ghz.

Bulldozer. More IPC than X4 in 4 threads or less, "less" distributed per "core" in 8.

Also, IPC is so far behind in Phenom II, why would we use STARS again? We are verging on 25-30% slower than Intel CPC, with a 15% frequency difference and new intel chips are doing 3.8 Ghz turbo, OCing to 4.8-5.0. We need a change. (If 5% IPC hit means 15-20% more clocks, I'm all for it tbh.)

You guys are so focused on multi-threaded results it's rediculous. Trying to predict single thread performance with a multithread benchmark is rediculous.

It's kind of like comparing a 2600K that does 5 Ghz on air to a 980X that does 4.3. Do you really want that 980X because its Cinebench score is higher, or would you like the extra single thread perf?

With no real CLEAR results WITH explanations out yet, I am still firm with my belief that in layman's terms, CMT = AMD HT in physical form that can not be turned off, trumping Intel's HT.

[HTC]

Any word on stable underclock potential yet? I'm referring to power savings, when compared to stock.

[Manicdan]

You guys seem to have missed what chew said...
1. Bulldozer functions like a 4 core that is able to execute 8 threads. You get roughly 5x scaling in CB from one to eight cores. (Better than HT) I don't care what PR tells you, that's how it works.
2. You have two options with the "STARS" core.
...Option 1. Shrink X6 (probably with redesigned Llano "STARS" core, so 3% IPC increase lets say) and increase frequency a tad. Lets say that this arch. will do 4.5 Ghz.
...Option 2. Add more cores, most likely decrease IPC from Thuban or keep it the same using Llano's tweaked core...lets say this arch will do 4.1 Ghz.

Bulldozer. More IPC than X4 in 4 threads or less, "less" distributed per "core" in 8.

no one knows the the exact scaling because its hidden behind NDA.
and if they did stick with PII architecture it would be more than 3% because llano does quite nicely for not having and L3. it would also pack in more true cores. by omitting the extra space used for the second thread of the module, the core itself got bigger with BD, so IPC should be higher or they found ways to waste more space. (btw your option 2 makes no sense, why reduce IPC since they can easily pack in 8 old cores in BDs size, and why would that drop the clocks by 400mhz)

i honestly dont believe in just 6pts for BD at 3.6ghz, and if that is the case its probably on the very low end of the spectrum for how it handles otherwise it would be a step backwards.

[freeloader]

Too bad AMD didn't update Thuban to a real 8 core 32nm processor. Give it a triple channel memory controller, more L3 cache (12MB+), faster L3 cache speed (3Ghz+) and a target speed of 4+GHz at launch.

[EniGmA1987]

Too bad AMD didn't update Thuban to a real 8 core 32nm processor. Give it a triple channel memory controller, more L3 cache (12MB+), faster L3 cache speed (3Ghz+) and a target speed of 4+GHz at launch.

Thats not an upgrade, thats an entirely new processor architecture

[BeepBeep2]

no one knows the the exact scaling because its hidden behind NDA.
and if they did stick with PII architecture it would be more than 3% because llano does quite nicely for not having and L3. it would also pack in more true cores. by omitting the extra space used for the second thread of the module, the core itself got bigger with BD, so IPC should be higher or they found ways to waste more space. (btw your option 2 makes no sense, why reduce IPC since they can easily pack in 8 old cores in BDs size, and why would that drop the clocks by 400mhz)

i honestly dont believe in just 6pts for BD at 3.6ghz, and if that is the case its probably on the very low end of the spectrum for how it handles otherwise it would be a step backwards.

Maybe I'm the stupid one here...
Llano's IPC difference vs Propus is neglegible. It's worth about 100 Mhz...or roughly 3%. Sure, up to 5% in some apps...too bad we are 30% behind Sandy with "STARS". As far as AMD's efficiency falling with more cores? Yeah. Thuban is a slower CPU in single thread than Deneb (partially due to less cache)...but look it up.

I leave you with a long string of quotes from chew in this thread that were posted in reaction to BD's leaked performance, ending with a response to freeloader:
By the way, VR-Zone Cinebench leak has shown ~5x scaling over all cores from single thread (not one whole module-core like the patent design states)
Regardless of what is behind NDA and what is not, between what we have for current leak and what chew* has said, I expect scaling from 5.0 to 5.5x on retail chips.

I see it as a 4 core part that can execute up to 8 threads, An engineer at AMD while I was there tended to agree with me, but what does he know.........

We obviously have members here that know more about BD than AMD.

Thuban had the same tdp but lost effeciency core per core to deneb if you guys all forgot about that, so you shrink it maybe increase ipc which will increase tdp somewhat.......you can do one of two things, scale clocks and be right back at same tdp or add two more cores, sacrifice scaling, that's really not an option.

An 8 core thuban would have been damn close to gulfy in multithreaded however.

Said it before and will say it again.

TDP.........

If you shrunk thuban to 32nm you could do 1 of 2 things, add 2 cores or increase clocks......not both, there's no room to grow.

Apparently according to AMD's roadmap however with bulldozer there is room to grow and stay within TDP limitations......

*insert flank3r post about how X8 would be a multithreading beast*

...I've been claiming far before bulldozer talk how well "STARS" does multithreaded, if multithread was AMD's focus they should have stayed with it in my opinion. On 45nm, it was very competetive with Lynnfield and Bloomfield multithreaded.

Maybe but you missed the other part i mentioned.........Where do you go from there.

You have no room to grow so your back to square 1 and need a new architecture to build on.

Wow someone with common sense...........

Like i said before I discussed this face to face with engineers at AMD, BD is a native 4 core 8 thread part.

and then the lynch mob got mad..........

I'm just gonna put this little bit out there.

There is more than 1 way to skin a cat.

Why is there still an on going discussion of core's modules.........

I don't give a rats ass what Marketing calls the chip.

AMD's patent draws a clear picture. They say a picture says a 1000 words right? AMD's own picture for there own patent.

Note core 100 not module 100 aka core 0, and then inside core 0 is 2 clusters A and B.

Case closed.

Only reason I have tried to point this out many times so far is due to peoples expectations. Those expecting 100% native 8 core multithreaded performance have unrealistic expectations. Hopefully this gives them a better idea so they can have more realistic expectations.

Engineers > Marketing when it comes to what's really what.

It's microcode injected into a bios.

For every cpu generation and or revision the microcode can be tuned/optimized and even without a silicon revision.

From there board partners can play around and "tweak" it even more via bios.

There are many bios options that can effect the outcome of benches.

HPET is 1 for example, it stops the cpu from throttling back in mulithreaded apps.

Running pi on a cluster, versus a core ( 2 threads ) versus being able to disable a single cluster in a core ( which 99% boards/bios's do not have implemented so resources are not shared ) can all influence the results in single threaded.

Knowing all this tells you one thing for sure, you can make it look worse or make it look better all depending on your knowledge of the chip and or your intentions.

As far as PI it's an antiquated bench and has not been AMD's strong point for quite some time.

Granted some results shown tend to lead to the fact that 1m times are bad but looking at the bigger picture we also know that in many cases you can validate 1000mhz higher in many cases with BD, which would point to the fact that you can run 1m at alot faster speeds than current AMD tech.

Things that make you go hmm like what kind of times will we see at 8 gig or even comparing BD to deneb/thuban when same cooling is used.

*insert more arguements about how ty BD is and its not 4 cores blah blah, cinebench sucks it sucks blah blah*

Actually it's not. For whatever reason amd chose to market it as cores.

In reality however BD is more akin to 4 cores / 8 threads as they share resources.

I have said this since the beginning.

There are however other reasons for calling them cores.

Example you can disable HT with intel.

AMD's design to my knowledge however does not allow for disabling a core in a module, I could be wrong however.

These ARE cores in Zambezi. It is from hardware and software perspective a true 8 core processor.Each module can retire 8 macroops per cycle(4 per core). Each core has a dedicated FMAC (And an additional FMAC if opportunity arises). The fact that cores share certain parts is because this is a smart thing to do from engineering POV. You save space and improve performance and perf./watt.
In the end,why would consumers even care? If it performs like an 8 core processor for all intents and purposes,why wouldn't people refer to it as to an 8 core processor(even if they don't personally think it is one)?

...some example talk, because PR said it was true and the website said it was true, and AMD has a habit of either
A. Not talking to public
B. Talking to public (not us enthusiasts directly...like Simon) in horrible ways, misleading info, cheesy presentations, how Denebs with disabled cores are a "True Dual Core Design?"

There is no debate about how many it has. AMD has designated 8 so 8 it is........

Regardless of all those specs, docs and whitepapers you can dredge up I am telling people how it works.

If they wish to not accept that fact.....well thats their problem.

Too bad AMD didn't update Thuban to a real 8 core 32nm processor. Give it a triple channel memory controller, more L3 cache (12MB+), faster L3 cache speed (3Ghz+) and a target speed of 4+GHz at launch.

I'd give that CPU a launch speed of 3 Ghz. New processes, GF lagging behind and seemingly sucking at yields looks like trouble with new process.
As far as 12MB of cache...triple channel memory controller, two more cores...about 45-50% more die space (rough estimate, larger DDR3 controller + reorder cores for 3+3+2 and AMD's horrible cache density equalling 15% of Thubans die (6MB)) on a 40% shrink so you are looking at 5% larger than thuban around 350-375 mm^2? Leaves no room at all to grow, even if they could pull that off.

[dess]

CMT = AMD HT in physical form that can not be turned off, trumping Intel's HT.

Don't call it HT, in relation to AMD, please. HyperThreading is a brandname of Intel for its implementations of SMT.
So, CMT is a kind of Multi Threading. A quite different one to SMT. Otherways both are "physical".

I agree that it's a 4-core + CMT, from engineering POV. Altough, if it performs comparably to a true 8-core of earlier uarch's, then it can be valid to call it a 8-core.