AMD Zambezi news, info, fans !

[danielkza]

drfedja great work, I love these diagrams. If you don't mind I will link them to another forum I frequently visit.

I'd be even more thankful if there happened to be a version in English.

[drfedja]

BTW you interpret the Address Generation Units as units for calculate linear addresses as well as INC/LEA values. The Optimization Guide refers them as simple integer exetution units, too (AGLU).

Would you briefly explain what kind of operations can these units execute?

Thanks

Also I'd like to know what type of instructions can execute AGLU, but what my knowledge of what can AGLU execute is based also on Optimisation Manual and my assumptions is that the AGLU can execute address calculations and LEA, and probably can execute INC. If AMD's manual says that the AGLU can execute simple ALU operations. Maybe i'm wrong for INC, but it could be possible for such unit to support some other type of instructions than CALL and LEA.
If it can calculate adress, that unit can also execute simple ADD or INC with unsigned integer (address + offset) and some logical operations like XOR or AND. That is my speculation, because Optimisation Manual probably isn't fully written.

Optimisation guide also refer this:

There are four integer execution units per core. Two units which handle all arithmetic, logical and
shift operations (EX). And two which handle address generation and simple ALU operations
(AGLU). Figure 2 shows a block diagram for one integer cluster. There are two such integer clusters
per compute unit.

Optimisation manual says that the AG0|AG1 units execute LEA instruction when work with 3 operands. But with legacy 2 operand instructions LEA can be executed only at EX0|EX1 units. AG0|AG1 can execute CALL instructions, which is double op decoded. Fist op. execute on EX and secon op. execite on AGLU.
The CALL instruction clearly transfers control to another procedure, and the RET instruction returns to the instruction following the call.
But that isn't any big difference in comparison to K10. K10 also execute CALL instruction like double op, but on BD CALL disp, near and CALL reg, near has 50% lower latency than 10h and CALL mem (near) is hardwired - double decoded, on 10h is microcoded.

According to Optimisation manual, main difference in BD AGU vs 10h AGU units is that the BD AGU can execute LEA, when work with three operands, and CALL is fully hardwired, with slightly lower latencies.

I'd be even more thankful if there happened to be a version in English.

Use google translate to learn Serbian... :P
I will translate that diagrams to English, that isn't problem, but I think it is understandable in that version. Picture is worth a thousand words! :P

[cal_guy]

drfedja awesome looking diagrams, however I think there's a small error for the Bulldozer FPU. Bulldozer only has 1 IMAC unit and it's located in Pipe 0 which it shares with an FMA unit and a convert unit. The two integer units in pipe 2 and pipe 3 are for vector integer ADD(multiplication is done in the IMAC unit) as well as AVX, SSE and x87 instructions that are not handled by the FMA, CVT, or the XBR units.

[drfedja]

You are right. I will correct that.
There are no 256-bit integer AVX instructions (256-bit int. AVX comes with AVX2) and integer FMA is handled by FP pipe 0.

According to Optimisation Manual:

A 128-bit integer multiply accumulate (IMAC) unit is incorporated into FPU pipe 0. The IMAC
performs integer fused multiply and accumulate, and similar arithmetic operations on AVX, MMX
and SSE data. A crossbar (XBAR) unit is integrated into FPU pipe 1 to execute the permute
instruction along with shifts, packs/unpacks and shuffles. There is an FPU load-store unit which
supports up to two 128-bit loads and one 128-bit store per cycle.

All of them can execute integer SIMD instructions. Pipe 0 performs integer fused multiply accomulate, and pipe 1 execute shuffle and FSTORE and all of integer SIMD.

There are four units. According to instruction latencies table, CVT unit is pipe 0, which is shared with FMA0 pipe 0 (128-bit FP block), pipe 1 is XBAR unit which is responsible for shuffling operations and shared with FMA1, pipe 2 and pipe 3 is integer SIMD units which handle some bitwise or logic operations: eg.
ANDNP, ANDNS is FP bitwise operations but it is handled by pipe 2 and pipe 3. That type of instructions has same troughput on 10h, but there is shared with FADD or FMUL pipe.

[undone]

The thread's becoming more & more technical. I still wonder whether bulldozer could use all of the four FPU unit(128bit*2 fmac+ 128bit*2 mmx) to run superpi.

[drfedja]

SuperPi uses about 50% of legacy x87 FP operations. Average IPC of SPi is 0.65-0.7 with 10h microcarchitecture. SPi is mixed type of code, and it is very memory depended, because there is alot of memory stack operations. In general, FPU throughput isn't bottleneck for executing SPi. x87 execution of SPi is saturated by inefficiency of 10h memory subsystem (LS-units->L1D->L2->L3 caches). I think that SPi could be much better on BD, but significantly slower than Sandy or even Nehalem.
In general, SPi isn't optimised code for modern parallel SIMD architecture. There aslo could be problem with unaligned memory access, store to load forwarding and data dependencies in order to run code serialized. That is probably the main reason why is Core architecture so superior when runing such unoptimized code.

[Oliverda]

Thanks, so there is no newer information about AGLUs.

My speculation: if the AGLUs can handle any of the ALU operations, then they must know normal, zero and sign-extended register copy at least, so the instruction table is inaccurate. The additions also must be handled by them and with a slightly more compexity the SUB, NEG, INC, DEC and CMP operations (not the fused compares, just the standalone ones). The logical NOTs, ANDs, ORs, XORs and (not fused) TESTs also requires only a little more simple circuits.

And exaclty these operations are performed by the double-pumped fast ALUs in Netburst, at 4/cycle rate.

[drfedja]

Thanks, so there is no newer information about AGLUs.

My speculation: if the AGLUs can handle any of the ALU operations, then they must know normal, zero and sign-extended register copy at least, so the instruction table is inaccurate. The additions also must be handled by them and with a slightly more compexity the SUB, NEG, INC, DEC and CMP operations (not the fused compares, just the standalone ones). The logical NOTs, ANDs, ORs, XORs and (not fused) TESTs also requires only a little more simple circuits.

And exaclty these operations are performed by the double-pumped fast ALUs in Netburst, at 4/cycle rate.

Maybe, some people on the Net had speculated that simple ALU or AGLU on BD may handle instructions like 30 years old 6502.

However, mov, push and call are most frequent instructions in x86 machine code. Also the SUB, NEG, INC, DEC and CMP is often used, so AGLU unit could be very useful.

Attachment 118788

[Oliverda]

Maybe, some people on the Net had speculated that simple ALU or AGLU on BD may handle instructions like 30 years old 6502.

However, mov, push and call are most frequent instructions in x86 machine code. Also the SUB, NEG, INC, DEC and CMP is often used, so AGLU unit could be very useful.

I think the MOV section covers simple loads, stores (certain workplace of AGUs) and register copies on the picture. Since the PUSH and POP instructions has been already recuced to single store and load operations at execution level by the K10's Stack Engine, they had to look for another instruction group to speed up (my mentioned conception could extend the general integer execution speed from K10's 3 to 4 ALU operations/cycle/thread). Many conditional jumps (je, jne and others) will be fusioned with preceding TEST/CMP instruction, so the listed add-like and logical ALU instructions would cover another 10-12% on the picture by the AGLU-s.

[Mats]

http://www.xbitlabs.com/news/coolers..._Solution.html

[Manicdan]

http://www.xbitlabs.com/news/coolers..._Solution.html

good idea for cpus that are ONLY expensive since people buying such chips cant really do anything about it. but for chips in the 300-400$ range its going to deter people who dont need the nice heatsink unless they also have the regular versions also available with a discount.

[slaveondope]

AMD Considers Equipping FX Chips with Liquid-Cooling Solution
http://www.xbitlabs.com/news/coolers..._Solution.html

Intel Considers to Bundle Liquid Cooling Solution with Next-Generation Enthusiast Processors
http://www.xbitlabs.com/news/coolers...rocessors.html

[xVeinx]

That is an interesting concept, but then they have to deal with potential for RMA. Having a fan fail on a inexpensive heatsink isn't the same, or as likely, as having the pump fail on the water-cooling unit. Kind of a cool idea, but I'd be afraid it would come back to haunt them in the long term.

[muziqaz]

I had Coolit sealed water systems pump pop. It took the whole system except cpu(5870, AM3 motherboard). I would imagine that if AMD went this way, they would use one of those sealed systems as they are cheapest. If a air cooler fails, you have system shut down or freeze, if water cooler fails, you have quite a bit of damage.

[Manicdan]

all alienware PCs come with these now, so i bet they are reliable enough to use with other products too

[thematrixhazune]

would AMD manufacture them or farm them out?

[BeepBeep2]

would AMD manufacture them or farm them out?

Farm them out. AMD doesn't even manufacture their own CPUs....

[FlanK3r]

I think, it will be good idea. The topmodel CPU bundled with some better aircooler (Tower type) or lowend WT setup as H50 or H70....

[freeloader]

http://www.amdzone.com/phpbb3/viewto...rt=900#p209349

Starting to look like BD is a total dud. Sorry, it hurts me to say this but I believe OBR is correct. I just hope I didn't wast $230 CDN on a Crosshair V mobo.

BD = DNF of processors. ???

[Hondacity]

nice i'll see lots of highend boards going for cheap

[LightSpeed]

Ill wait till the end of October before I slowly start losing faith in BD. I hope that day never comes.

[muziqaz]

http://www.amdzone.com/phpbb3/viewto...rt=900#p209349

Starting to look like BD is a total dud. Sorry, it hurts me to say this but I believe OBR is correct. I just hope I didn't wast $230 CDN on a Crosshair V mobo.

BD = DNF of processors. ???

If it's true it means there is a problem with yields. It does not mean that BD has bad performance of some sorts.

[demonkevy666]

http://www.amdzone.com/phpbb3/viewto...rt=900#p209349

Starting to look like BD is a total dud. Sorry, it hurts me to say this but I believe OBR is correct. I just hope I didn't wast $230 CDN on a Crosshair V mobo.

BD = DNF of processors. ???

If Orb is correct. I'm magical.

[undone]

If it's true it means there is a problem with yields.

It's capacity problem, which occured with old 90nm X2.

[muziqaz]

It's capacity problem, which occured with old 90nm X2.

I think everyone especially AMD would be happy to sell as much as they did in 90nm days