I made some small progress. I found out that a tRCD of nine with a CAS Write Latency of 8 over DDR3-1600 causes the reboot cycles. Chaning tCWL to 9 instead causes a hang with the DRAM LED lit up. The other subtimings don't make any difference at all: I relaxed CAS Write Latency, Write Recovery Time and Read to Pre Time up to 12, and DRAM RTL up to 40, and nothing changed. The funny thing is with a tRCD of 10, CAS Write Latency of 9 and above also causes the hang. Maybe it's my RAM after all?
Here are the subtimings set by the board, with XMP and 2133 9-10-9-28, respectively.
Code:
* Primary Timings *
DRAM CAS# Latency: 7
DRAM RAS# to CAS# Delay: 8
DRAM RAS# PRE Time: 7
DRAM RAS# ACT Time: 24
DRAM COMMAND Mode: 2
* Secondary Timings *
DRAM RAS# to RAS# Delay: 5
DRAM REF Cycle Time: 88
DRAM Refresh Interval: 6240
DRAM Write Recovery Time: 10
DRAM READ to PRE Time: 6
DRAM FOUR ACT WIN Time: 24
DRAM WRITE to READ Delay: 6
DRAM CKE Minimum pulse width: 4
DRAM CAS# Write Latency: 7
DRAM RTL(CHA): D0: 32, D1: 33
DRAM RTL(CHB): D0: 32, D1: 34
Code:
* Primary Timings *
DRAM CAS# Latency: 9
DRAM RAS# to CAS# Delay: 10
DRAM RAS# PRE Time: 9
DRAM RAS# ACT Time: 28
DRAM COMMAND Mode: 2
* Secondary Timings *
DRAM RAS# to RAS# Delay: 7
DRAM REF Cycle Time: 118
DRAM Refresh Interval: 8139
DRAM Write Recovery Time: 10
DRAM READ to PRE Time: 9
DRAM FOUR ACT WIN Time: 33
DRAM WRITE to READ Delay: 9
DRAM CKE Minimum pulse width: 6
DRAM CAS# Write Latency: 8
DRAM RTL(CHA): D0: 32, D1: 39
DRAM RTL(CHB): D0: 32, D1: 40
Originally Posted by danielkza
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